FAN53540 Fairchild Semiconductor, FAN53540 Datasheet - Page 12

• Manufacturer Part Number: FAN53540
• Description: The FAN53540 is a step-down switching voltage regulator that delivers an adjustable output from an input voltage supply of 2
• Manufacturer: Fairchild Semiconductor

© 2011 Fairchild Semiconductor Corporation
FAN53540 • Rev. 1.0.2
Output Capacitor and V
Table 1 suggests 0805 capacitors, but 0603 capacitors may
be used if space is at a premium. Due to voltage effects, the
0603 capacitors have a lower in-circuit capacitance, which
can degrade transient response and output ripple.
Increasing C
can be increased to reduce output voltage ripple or to
improve transient response. Output voltage ripple, ∆V
where C
capacitance of C
which results in higher ∆V
C
value greater than 1.0H is used, at least 30F of C
should be used to ensure transient response performance.
The lowest ∆V
and, therefore, operating at 2.4MHz. In PFM Mode, f
reduced, causing ∆V
ESL Effects
The Equivalent Series Inductance (ESL) of the output
capacitor network should be kept low to minimize the square-
wave component of output ripple that results from the division
ratio C
wave component due to the ESL can be estimated as:
A good practice to minimize this ripple is to use multiple
output capacitors to achieve the desired C
example, to obtain C
produce twice the square wave ripple of two 10F 0805.
To minimize ESL, try to use capacitors with the lowest ratio
of length to width. 0805s have lower ESL than 1206s. If very
low output ripple is necessary, research vendors that
produce 0508 or 0612 capacitors with ultra-low ESL. Placing
additional small value capacitors near the load also reduces
the high-frequency ripple components.
Input Capacitor
The 10F ceramic input capacitor should be placed as close
as possible between the VIN pin and PGND to minimize the
parasitic inductance. If a long wire is used to bring power to
the IC, additional “bulk” capacitance (electrolytic or tantalum)
should be placed between C
reduce under-damped ringing that can occur between the
inductance of the power source leads and C
The effective C
increases due to DC bias effects. This has no significant
impact on regulator performance.
To reduce ringing and overshoot on VIN and SW, an
additional bypass capacitor C
this lower value capacitor has a higher resonant frequency
than C
pins of the IC than C


V
OUT
V
OUT
OUT
, the regulator may fail to start under load. If an inductor
OUT
IN

(
; C
SQ

OUT
I
ESL and the output inductor (L

IN1
)




OUT

8
OUT
should be placed closer to the VIN and GND
is the effective output capacitance. The
V

C
has a negligible effect on loop stability and
IN
IN
OUT
OUT
is obtained when the IC is in PWM Mode

1
IN
OUT
capacitance value decreases as V
ESL
OUT
.
decreases at higher output voltages,

f
to increase.
SW
=20F, a single 22F 0805 would
L
COUT
1
OUT

IN
ESR
IN1
. If large values are used for
OUT
and the power source lead to
is recommended. Because




Ripple
OUT
IN
.
OUT
). The square-
value. For
OUT
SW
, is:
(9)
OUT
(8)
is
IN
12
Layout Recommendations
The layout example below illustrates the recommended
component placement and top copper (green) routing. The
inductor in this example is the TDK VLC5020T-R47N.
To minimize VIN and SW spikes and thereby reduce voltage
stress on the IC’s power switches, it is critical to minimize the
loop length for the VIN bypass capacitors.
Switching current paths through C
returned directly to the GND bumps of the IC on the top
layer of the printed circuit board (PCB). VOUT and GND
connections to the system power and ground planes can
be made through multiple vias placed as close as possible
to the C
close to its load as possible to minimize trace inductance
and capacitance.
Connect the VOUT pin and R1 directly to C
impedance path (shown in red in Figure 28. Recommended
Layout). A >0.4mm wide trace is recommended. Avoid
routing this trace directly beneath SW unless separated by
an internal GND plane.
If the MODE function is not required, extend the ground
plane through the MODE pin to reduce the loop inductance
for the VIN bypass.
Thermal Considerations
Heat is removed from the IC through the solder bumps to the
PCB copper. The junction-to-ambient thermal resistance
(
weight, and trace width) and the temperature rise from
junction to ambient (T).
For the FAN53540UC, 
four-layer evaluation board in still air, with 2oz. outer layer
copper weight and 1oz. inner layers. Halving the copper
thickness results in an increased 
For long term reliable
temperature (T
Maximum IC power loss is 2.88W. Figure 29 shows required
power dissipation and derating for a FAN53540UC mounted
on the Fairchild evaluation board in still air (38°C/W).
JA
) is largely a function of the PCB layout (size, copper
OUT
capacitors. The regulator should be placed as
Figure 28. Recommended Layout
J
) should be maintained below 125°C.
JA
is 38°C/W when mounted on its
operation,
JA
IN
of 48°C/W.
and C
the
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OUT
OUT
IC’s
using a low
should be
junction