FAN21SV06 Fairchild Semiconductor, FAN21SV06 Datasheet - Page 13

• Manufacturer Part Number: FAN21SV06
• Description: This part is covered in Fairchild's href="http://www
• Manufacturer: Fairchild Semiconductor

© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.1
Protections
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, and under-
voltage conditions.
Under-Voltage Protection
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This fault is prevented from
setting the fault latch during soft-start.
Over-Voltage Protection
If FB exceeds 115%
cycles, the fault latch is set and shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
These two fault conditions are allowed to set the fault
latch at any time, including during soft-start.
Over-Temperature Protection
The chip incorporates an over-temperature-protection
circuit that sets the fault latch when a die temperature of
about 155°C is reached. The IC is allowed to restart
when the die temperature falls below 125°C.
EN / Auto-Restart
After a fault, EN pin is discharged with 1µA current pull
down to a 1.1V threshold before the internal 800k pull
up is restored. A new soft-start cycle begins when EN
charges above 1.35V.
Depending on the external circuit, the FAN21SV06 can
be configured to remain latched off or automatically
restart after a fault, as listed in Table 1.
Table 1. Fault / Restart Configurations
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin high with a
logic gate to keep the 1µA current sink from discharging
EN to 1.1V. Figure 31 shows one method to pull up EN
to V
EN pin
Pull to GND
Connected to
5V_Reg
Open
Cap to GND
CC
for a latch configuration.
Controller / Restart State
Standby
No restart – latched OFF
Immediate restart after fault
New soft-start cycle after:
EN is HIGH (Auto Restart Mode)
•
V
REF
for two consecutive clock
13
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW when
V
The
Specifications section. PGOOD does not assert HIGH
until soft start is complete (T1.0).
Application Information
Setting the Output Voltage
The output voltage of the regulator can be set from 0.8V
to ~80% of V
R
current rating may need to be de-rated depending on the
ambient temperature, power dissipated in the package
and the PCB layout. (Refer to Thermal Information table
and Figure 29.)
The internal reference is set to 0.8V with 650nA sourced
from the FB pin to ensure that the regulator does not
start if the pin is left open.
The external resistor divider is calculated using:
Connect R
Setting the Clock Frequency
Oscillator frequency is determined by a resistor, R
connected between the (R
or 5V_Reg (Slave Mode):
where R
where frequency (f) is expressed in KHz. In slave mode,
the switching frequency is about 10% slower for the
same R
The regulator does not start if R
mode.
f
R
R
(
0
OUT
KHz
BIAS
T
BIAS
8 .
(
Figure 31.
K
V
)

is out of regulation, as measured at the FB pin.
in Figure 1). For output voltages >3.3V, output

thresholds
)


T
(
T
.
65
(
V
is expressed in k.
10
BIAS
OUT

6
R
10
IN
/
between FB and AGND.
R
T
65
f

6
by an external resistor divider (R1 and
1
)
)
Enable Control with Latch Option
0


8 .
135
135
are
V

650
specified
T
)pin and AGND (Master Mode)
nA
T
in
is open in Master
the
www.fairchildsemi.com
Electrical
T,
that is
(1)
(2)
(3)