TLE 4267G Infineon Technologies, TLE 4267G Datasheet - Page 3
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TLE 4267G
Manufacturer Part Number
TLE 4267G
Description
Manufacturer
Infineon Technologies
Datasheet
1.TLE_4267.pdf
(23 pages)
Specifications of TLE 4267G
Packages
PG-TO263-7
Regulator Type
single output
Output Voltage
5V
Accuracy
2.0 %
Max. Output Current
400mA
Dropout Voltage
300mV
Application
The IC regulates an input voltage
voltage of
4.5 V). The reset delay can be set with an external capacitor. The device has two logic
inputs. A voltage of
Depending on the voltage on pin E6 the IC may be hold in active-state even if
to low level. This makes it simple to implement a self-holding circuit without external
components. When the device is turned off, the output voltage drops to 0 V and current
consumption tends towards 0 μA.
Design Notes for External Components
The input capacitor
circuit consisting of lead inductance and input capacitance can be damped by a resistor
of approx. 1 Ω in series with
regulating circuit. Stability is guaranteed at values of ≥ 22 μF and an ESR of ≤ 3 Ω within
the operating temperature range.
Circuit Description
The control amplifier compares a reference voltage, which is kept highly accurate by
resistance adjustment, to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load
current prevents any over-saturating of the power element.
The reset output RO is in high-state if the voltage on the delay capacitor
equal
greater than the reset threshold
discharge of the delay capacitor
reset output RO is set to low-level (see
range by dimensioning the capacitance of the external capacitor.
Data Sheet
V
UD
. The delay capacitance
V
Q
= 5.0 V. A reset signal is generated for an output voltage of
V
C
E2
I
is necessary for compensation of line influences. The resonant
> 4.0 V given to the E2-pin (e.g. by ignition) turns the device on.
C
I
. The output capacitor is necessary for the stability of the
C
V
V
D
C
I
RT
in the range of 5.5 V <
sets in and as soon as
D
. If the output voltage gets lower than
is charged with the current
Figure
3
6). The reset delay can be set within wide
V
V
I
CD
< 40 V to a nominal output
gets lower than
I
D
Rev. 2.51, 2012-01-20
for output voltages
C
V
D
Q
is greater or
TLE 4267
<
V
V
RT
V
E2
V
RT
a fast
LD
goes
(typ.
the