IFX1040SJ Infineon Technologies, IFX1040SJ Datasheet - Page 10

• Manufacturer Part Number: IFX1040SJ
• Manufacturer: Infineon Technologies

Specifications of IFX1040SJ

• Packages: PG-DSO-8
• Transmission Ratemax: 1.0 Mbit/s
• Bus Wake-up Capability: Yes
• Additional Features: STB, WK, SPLIT
• Wake-up Inputs: Bus wake-up
• Standards: ISO 11898-2/ISO11898-5

Split Circuit
The split circuitry is activated during normal mode and deactivated (SPLIT pin floating) during standby mode. The
SPLIT pin is used to stabilize the recessive common mode signal in normal mode. This is realized with a stabilized
voltage of 0.5 V
A correct application of the SPLIT pin is shown in
realized with two 60 Ω resistances and one 10 nF capacitor. The center node in this example is a stub node and
the recommended value for the split resistances is 1.5 kΩ.
Figure 7
Other Features
Fail Safe
If the device is supplied but there is no signal at the digital inputs, the TxD and STB have an internal pull-up path,
to prevent the transceiver to switch into the normal mode or send a dominant signal on the bus.
Un-supplied Node
The CANH/CANL pins remain high ohmic, if the transceiver is un-supplied.
Data Sheet
IFX1040
Application of the SPLIT Pin for Normal Nodes and one Stub Node
CC
CANH
SPLIT
CANL
at SPLIT.
10
nF
Split
Termination
at Stub
60
Split
Termination
60
Ω
Ω
CANH
1.5
Figure
kΩ
CAN
Bus
IFX1040
10
SPLIT
7. The split termination for the left and right node is
1.5
10
nF
kΩ
Split
Termination
CANL
60
60
Ω
Ω
10
nF
Application Information
CANH
SPLIT
CANL
Rev. 1.0, 2011-11-4
IFX1040
IFX1040