ADV7392BCPZ Analog Devices, ADV7392BCPZ Datasheet
ADV7392BCPZ
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ADV7392BCPZ Summary of contents
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... Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...
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ADV7390/ADV7391/ADV7392/ADV7393 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Detailed Features .............................................................................. 4 General Description ......................................................................... 4 Specifications..................................................................................... 5 Power Supply Specifications........................................................ 5 Input Clock Specifications .......................................................... 5 Analog Output Specifications..................................................... ...
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Appendix 3–SD Closed Captioning..............................................70 Appendix 4–Internal Test Pattern Generation ............................71 SD Test Patterns...........................................................................71 ED/HD Test Patterns ..................................................................71 Appendix 5–SD Timing..................................................................72 Appendix 6–HD Timing ................................................................77 Appendix 7–Video Output Levels.................................................78 SD YPrPb Output Levels—SMPTE/EBU N10 ........................78 ED/HD YPrPb Output Levels ...................................................79 REVISION ...
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ADV7390/ADV7391/ADV7392/ADV7393 DETAILED FEATURES High definition (HD) programmable features (720p/1080i/1035i) 4× oversampling (297 MHz) Internal test pattern generator Color and black bar, hatch, flat field/frame Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control ...
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SPECIFICATIONS POWER SUPPLY SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 2. Parameter SUPPLY VOLTAGES DD_IO POWER SUPPLY REJECTION RATIO INPUT CLOCK SPECIFICATIONS V = 1.71 ...
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ADV7390/ADV7391/ADV7392/ADV7393 DIGITAL INPUT/OUTPUT SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 5. Parameter Input High Voltage, ...
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DIGITAL TIMING SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 7. Parameter VIDEO DATA AND VIDEO ...
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ADV7390/ADV7391/ADV7392/ADV7393 VIDEO PERFORMANCE SPECIFICATIONS Table 8. Parameter STATIC PERFORMANCE Resolution 1 Integral Nonlinearity (INL Differential Nonlinearity (DNL) STANDARD DEFINTION (SD) MODE Luminance Nonlinearity Differential Gain Differential Phase 3 Signal-to-Noise Ratio (SNR) ENHANCED DEFINITION (ED) MODE Luma Bandwidth Chroma ...
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TIMING DIAGRAMS The following abbreviations are used in Figure 2 to Figure 9. • Clock high time 9 • Clock low time 10 • Data setup time 11 • Data hold time ...
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ADV7390/ADV7391/ADV7392/ADV7393 CLKIN CONTROL HSYNC INPUTS VSYNC Y0 PIXEL PORT Cb0 PIXEL PORT CONTROL OUTPUTS CLKIN CONTROL HSYNC INPUTS VSYNC PIXEL PORT PIXEL PORT PIXEL PORT CONTROL OUTPUTS CLKIN* CONTROL HSYNC INPUTS VSYNC PIXEL PORT CONTROL OUTPUTS ...
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CLKIN PIXEL PORT 3FF CONTROL OUTPUTS *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 7. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010 CLKIN ...
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ADV7390/ADV7391/ADV7392/ADV7393 Y OUTPUT HSYNC VSYNC PIXEL PORT PIXEL PORT PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A ...
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Y OUTPUT b HSYNC VSYNC PIXEL PORT PIXEL PORT PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A ...
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ADV7390/ADV7391/ADV7392/ADV7393 HSYNC VSYNC PIXEL PORT SDA SCL SPI_SS SPI_SS SCLK t 5 MOSI MISO Figure 14. SD Input Timing Diagram (Timing Mode 1) t ...
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ABSOLUTE MAXIMUM RATINGS Table 10. 1 Parameter V to AGND DGND PGND GND_IO DD_IO DD_IO DD AGND to ...
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ADV7390/ADV7391/ADV7392/ADV7393 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS V 1 DD_IO PIN INDICATOR ADV7390 ADV7391 DGND 6 TOP VIEW P5 7 (Not to Scale Figure 17. ADV7390/ADV7391 Pin Configuration Table ...
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Pin Number Mnemonic ADV7390/91 ADV7392/ EXT_LF 15 21 PGND 18 24 AGND DGND 32 40 GND_IO enhanced definition = 525p and 625p. 2 LSB = least significant bit. In the ADV7390, ...
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ADV7390/ADV7391/ADV7392/ADV7393 TYPICAL PERFORMANCE CHARACTERISTICS ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 19. ED 8× Oversampling, PrPb Filter (Linear) Response ...
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Y RESPONSE IN HD 4× OVERSAMPLING MODE 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 18.5 37.0 55.5 74.0 92.5 FREQUENCY (MHz) Figure 25. HD 4× Oversampling, Y Filter Response Y PASS BAND IN HD ...
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ADV7390/ADV7391/ADV7392/ADV7393 Y RESPONSE IN SD OVERSAMPLING MODE 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 31. SD 16× Oversampling, Y Filter Response 0 –10 –20 –30 –40 –50 –60 ...
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FREQUENCY (MHz) Figure 37. SD Luma QCIF Low-Pass Filter Response 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 38. ...
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ADV7390/ADV7391/ADV7392/ADV7393 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 43. SD Chroma CIF Low-Pass Filter Response Rev Page –10 –20 –30 –40 –50 –60 ...
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MPU PORT DESCRIPTION Devices such as a microprocessor can communicate with the ADV739x through one of the following protocols: • 2 2-wire serial (I C-compatible) bus • 4-wire serial (SPI-compatible) bus After power-up or reset, the MPU port is configured ...
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ADV7390/ADV7391/ADV7392/ADV7393 SDA SCL START ADDR R/W ACK SUBADDRESS ACK WRITE S SLAVE ADDR A(S) SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SEQUENCE S = START BIT P = STOP BIT SPI OPERATION The ADV739x supports a 4-wire serial ...
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REGISTER MAP A microprocessor can read from or write to all registers of the ADV739x via the MPU port, except for registers that are specified as read-only or write-only registers. The subaddress register determines the register accessed by the next ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 14. Register 0x01 to Register 0x09 SR7 to SR0 Register Bit Description 0x01 Mode Select Reserved. Register DDR Clock Edge Alignment. Note: Only used for ED HD DDR modes. Reserved. Input Mode. Note: See Reg. 0x30, Bits[7:3] for ...
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Table 15. Register 0x0B to Register 0x17 SR7 to SR0 Register Bit Description 0x0B DAC 1, DAC 2, Positive Gain to DAC Output Voltage. DAC 3 Output Level Negative Gain to DAC Output Voltage. 0x0D DAC Power DAC 1 Low ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 16. Register 0x30 SR7 to SR0 Register Bit Description 0x30 ED/HD Mode ED/HD Output Standard. Register 1 ED/HD Input Synchronization Format. ED/HD Input Mode. 1 Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs ...
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Table 17. Register 0x31 to Register 0x33 SR7 to SR0 Register Bit Description 0x31 ED/HD Mode ED/HD Pixel Data Valid. Register 2 HD Oversample Rate Select. ED/HD Test Pattern Enable. ED/HD Test Pattern Hatch/Field. ED/HD Vertical Blanking Interval (VBI) Open. ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 18. Register 0x34 to Register 0x38 SR7 to SR0 Register Bit Description 0x34 ED/HD Mode ED/HD Timing Reset. Register 5 ED/HD HSYNC Control. ED/HD VSYNC Control. Reserved. ED Macrovision Enable. Reserved. ED/HD VSYNC Input/Field Input. ED/HD Horizontal/Vertical Counter ...
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Table 19. Register 0x39 to Register 0x43 SR7 to SR0 Register Bit Description 0x39 ED/HD Mode Reserved. Register 7 ED/HD EIA/CEA-861B Synchronization Compliance. Reserved. 0x40 ED/HD Sharpness ED/HD Sharpness Filter Gain Filter Gain Value A. ED/HD Sharpness Filter Gain Value ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 21. Register 0x58 to Register 0x5D SR7 to SR0 Register 0x58 ED/HD Adaptive Filter Gain 1 0x59 ED/HD Adaptive Filter Gain 2 0x5A ED/HD Adaptive Filter Gain 3 0x5B ED/HD Adaptive Filter Threshold A 0x5C ED/HD Adaptive Filter ...
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Table 22. Register 0x5E to Register 0x6E SR7 to SR0 Register Bit Description 0x5E ED/HD CGMS Type B ED/HD CGMS Type B Register 0 Enable. ED/HD CGMS Type B CRC Enable. ED/HD CGMS Type B Header Bits. 0x5F ED/HD CGMS ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 23. Register 0x80 to Register 0x83 SR7 to SR0 Register Bit Description 0x80 SD Mode SD Standard. Register 1 SD Luma Filter. SD Chroma Filter. 0x82 SD Mode SD PrPb SSAF Filter. Register 2 SD DAC Output 1. ...
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Table 24. Register 0x84 to Register 0x87 SR7 to SR0 Register Bit Description 0x84 SD Mode SD VSYNC-3H. Register 4 SD SFL/SCR/TR Mode Select. SD Active Video Length. SD Chroma. SD Burst. SD Color Bars. SD Luma/Chroma Swap. 0x86 SD ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 25. Register 0x88 to Register 0x89 SR7 to SR0 Register Bit Description 0x88 SD Mode Reserved. Register 7 SD Noninterlaced Mode. SD Double Buffering. SD Input Format. SD Digital Noise Reduction. SD Gamma Correction Enable. SD Gamma Correction ...
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Table 26. Register 0x8A to Register 0x98 SR7 to SR0 Register Bit Description 0x8A SD Timing Register 0 SD Slave/Master Mode. SD Timing Mode. Reserved. SD Luma Delay. SD Minimum Luma Value. SD Timing Reset. 0x8B SD Timing Register 1 ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 27. Register 0x99 to Register 0xA5 SR7 to SR0 Register Bit Description 0x99 SD CGMS/WSS 0 SD CGMS Data. SD CGMS CRC. SD CGMS on Odd Fields. SD CGMS on Even Fields. SD WSS. 0x9A SD CGMS/WSS 1 ...
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SR7 to SR0 Register Bit Description 0xA4 SD DNR 1 DNR Threshold. Border Area. Block Size. 0xA5 SD DNR 2 DNR Input Select. DNR Mode. DNR Block Offset. Table 28. Register 0xA6 to Register 0xBB SR7 to SR0 Register Bit ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 29. Register 0xE0 to Register 0xF1 SR7 to 1 SR0 Register Bit Description 0xE0 Macrovision MV Control Bits. 0xE1 Macrovision MV Control Bits. 0xE2 Macrovision MV Control Bits. 0xE3 Macrovision MV Control Bits. 0xE4 Macrovision MV Control Bits. ...
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ADV7390/ADV7391 INPUT CONFIGURATION The ADV7390/ADV7391 supports a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7390/ADV7391 defaults to standard definition (SD) mode upon power-up. Table 30 provides an overview of all possible ...
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ADV7390/ADV7391/ADV7392/ADV7393 ADV7392/ADV7393 INPUT CONFIGURATION The ADV7392/ADV7393 supports a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7392/ADV7393 defaults to standard definition (SD) mode upon power-up. Table 31 provides an overview of all ...
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ENHANCED DEFINITION/HIGH DEFINITION Subaddress 0x01, Bits[6:4] = 001 or 010 YCrCb data can be input in a 4:2:2 format over an 8-/10-bit DDR bus or a 16-bit SDR bus. The clock signal must be provided on the ...
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ADV7390/ADV7391/ADV7392/ADV7393 OUTPUT CONFIGURATION The ADV739x supports a number of different output configurations. Table 32 to Table 34 lists all possible output configurations. Table 32. SD Output Configurations RGB/YPrPb Output Select 1 (0x02, Bit ...
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FEATURES OUTPUT OVERSAMPLING The ADV739x include an on-chip phase-locked loop (PLL) that allows for oversampling of SD, ED, and HD video data. By default, the PLL is disabled. The PLL can be enabled using Subaddress 0x00, Bit ...
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ADV7390/ADV7391/ADV7392/ADV7393 ED/HD TIMING RESET Subaddress 0x34, Bit 0 An ED/HD timing reset is achieved by setting the ED/HD timing reset control bit (Subaddress 0x34, Bit this state, the horizontal and vertical counters remain reset. When this ...
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COMPOSITE 1 VIDEO H/L TRANSITION COUNT START 128 RTC TIME SLOT 01 1 FOR EXAMPLE, VCR OR CABLE PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 ...
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ADV7390/ADV7391/ADV7392/ADV7393 Programming the F SC The subcarrier frequency register value is divided into four F registers as shown in the previous example. The four subcarrier frequency registers must be updated sequentially, starting with Subcarrier Frequency Register 0 and ending with ...
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FILTERS Table 38 shows an overview of the programmable filters available on the ADV739x. Table 38. Selectable Filters Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma ...
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ADV7390/ADV7391/ADV7392/ADV7393 ED/HD Sinc Compensation Filter Response Subaddress 0x33, Bit 3 The ADV739x includes a filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in ED/HD mode. This filter is enabled ...
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If RGB output is selected, the ED/HD CSC matrix scalar uses the following equations × × × Y − (GU × Pb) − (GV × Pr × ...
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ADV7390/ADV7391/ADV7392/ADV7393 SD HUE ADJUST CONTROL Subaddress 0xA0 When enabled, the SD hue adjust control register (Subaddress 0xA0) is used to adjust the hue on the SD composite and chroma outputs. This feature can be enabled using Subaddress 0x87, Bit 2. ...
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DOUBLE BUFFERING Subaddress 0x33, Bit 7 for ED/HD, Subaddress 0x88, Bit 2 for SD Double-buffered registers are updated once per field. Double buffering improves overall performance because modifications to register settings are not be made during active video, but take ...
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ADV7390/ADV7391/ADV7392/ADV7393 SD gamma correction is enabled using Subaddress 0x88, Bit 6. SD Gamma Correction Curve A is programmed at Subaddress 0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B is programmed at Subaddress 0xB0 to Subaddress 0xB9. Gamma correction ...
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ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS Subaddress 0x40, Subaddress 0x58 to Subaddress 0x5D There are three filter modes available on the ADV739x: sharpness filter mode and two adaptive filter modes. ED/HD Sharpness Filter Mode To enhance or attenuate the ...
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ADV7390/ADV7391/ADV7392/ADV7393 CH1 500mV REF A 500mV 4.00µs Figure 75. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application The ED/HD ...
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Figure 76. Input Signal to ED/HD Adaptive Filter Figure 77. Output Signal from ED/HD Adaptive Filter (Mode A) When changing the adaptive filter mode to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 78 can be obtained. ...
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ADV7390/ADV7391/ADV7392/ADV7393 Coring Gain Border—Subaddress 0xA3, Bits[3:0] These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values increments of 1/8. This factor is applied to ...
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SD ACTIVE VIDEO EDGE CONTROL Subaddress 0x82, Bit 7 The ADV739x is able to control fast rising and falling signals at the start and end of active video to minimize ringing. When the active video edge control feature is enabled ...
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ADV7390/ADV7391/ADV7392/ADV7393 EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or external synchronization signals provided on the HSYNC and VSYNC pins (see Table ...
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... LOW POWER MODE Subaddress 0x0D, Bits[2:0] For power sensitive applications, the ADV739x supports an Analog Devices, Inc. proprietary low power mode of operation. To utilize this low power mode, the DACs must be operating in full-drive mode (R = 510 Ω 37.5 Ω). Low power mode is SET L not available in low drive mode (R = 4.12 kΩ ...
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... VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER An output buffer is necessary on any DAC that operates in low drive mode (R = 4.12 kΩ 300 Ω). Analog Devices Inc. SET L produces a range of op amps suitable for this application, for example, the AD8061. For more information about line driver buffering circuits, see the relevant op amp data sheet ...
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CIRCUIT FREQUENCY RESPONSE 0 –10 MAGNITUDE (dB) –20 –30 PHASE (Degrees) –40 –50 GROUP DELAY (Seconds) –60 –70 –80 1M 10M 100M FREQUENCY (Hz) Figure 89. Output Filter Plot for SD, 16× Oversampling CIRCUIT FREQUENCY RESPONSE 0 –10 MAGNITUDE (dB) ...
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ADV7390/ADV7391/ADV7392/ADV7393 Power Supply Decoupling It is recommended that each power supply pin be decoupled with 10 nF and 0.1 μF ceramic capacitors. The and both V pins should be individually decoupled to DD_IO DD ground. The decoupling ...
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TYPICAL APPLICATION CIRCUIT FERRITE BEAD V DD_IO 33µF 10µF GND_IO GND_IO FERRITE BEAD PV DD 33µF 10µF PGND PGND FERRITE BEAD V AA 33µF 10µF AGND AGND FERRITE BEAD V DD 33µF 10µF DGND DGND ...
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ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 1–COPY GENERATION MANAGEMENT SYSTEM SD CGMS Subaddress 0x99 to Subaddress 0x9B The ADV739x supports copy generation management system (CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of the ...
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IRE +70 IRE 0 IRE –40 IRE 11.2µs +700mV 70% ± 10% 0mV –300mV 5.8µs ± 0.15µs 6T PEAK WHITE 500mV ± 25mV SYNC LEVEL 5.5µs ± 0.125µs +700mV REF 70% ± 10% 0mV –300mV 4T 3.128µs ± 90ns ...
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ADV7390/ADV7391/ADV7392/ADV7393 +700mV 70% ± 10% 0mV –300mV 4T 4.15µs ± 60ns +700mV 70% ± 10% 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION. +700mV 70% ±10% 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A ...
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APPENDIX 2–SD WIDE SCREEN SIGNALING Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B The ADV739x supports wide screen signaling (WSS) conforming to the ETSI 300 294 standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ...
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ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 3–SD CLOSED CAPTIONING Subaddress 0x91 to Subaddress 0x94 The ADV739x supports closed captioning conforming to the standard television synchronizing waveform for color transmission. When enabled, closed captioning is transmitted during the blanked active line time of Line 21 ...
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APPENDIX 4–INTERNAL TEST PATTERN GENERATION SD TEST PATTERNS The ADV739x is able to generate SD color bar and black bar test patterns. The register settings in Table 55 are used to generate an SD NTSC 75% color bar test pattern. ...
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ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 5–SD TIMING Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in ...
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DISPLAY 622 623 624 625 H F EVEN FIELD DISPLAY 309 310 311 312 H ODD FIELD F ANALOG VIDEO H F Mode 1—Slave Option (Subaddress 0x8A = this mode, the ...
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ADV7390/ADV7391/ADV7392/ADV7393 DISPLAY 622 623 624 625 HSYNC FIELD EVEN FIELD DISPLAY 309 310 311 312 HSYNC FIELD ODD FIELD Mode 1—Master Option (Subaddress 0x8A = this mode, the ADV739x can generate ...
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DISPLAY 522 523 524 525 HSYNC VSYNC DISPLAY 260 261 262 263 HSYNC VSYNC DISPLAY 622 623 624 HSYNC VSYNC EVEN FIELD DISPLAY 309 310 311 HSYNC VSYNC ODD FIELD Mode 2—Master Option (Subaddress 0x8A = ...
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ADV7390/ADV7391/ADV7392/ADV7393 HSYNC VSYNC PIXEL DATA Figure 112. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave) Mode 3—Master/Slave Option (Subaddress 0x8A = this ...
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APPENDIX 6–HD TIMING FIELD 1 1124 1125 VSYNC HSYNC FIELD 2 561 562 VSYNC HSYNC ADV7390/ADV7391/ADV7392/ADV7393 VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 115. 1080i HSYNC ...
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ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 7–VIDEO OUTPUT LEVELS SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV 300mV Figure 116. Y Levels—NTSC 700mV Figure 117. Pr Levels—NTSC 700mV Figure 118. Pb Levels—NTSC 700mV 300mV Figure 119. Y Levels—PAL 700mV Figure 120. Pr ...
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ED/HD YPrPb OUTPUT LEVELS EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 122. EIA-770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 ...
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ADV7390/ADV7391/ADV7392/ADV7393 SD/ED/HD RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars R 700mV/525mV 300mV G 700mV/525mV 300mV B 700mV/525mV 300mV Figure 126. SD/ED RGB Output Levels—RGB Sync Disabled R 700mV/525mV 300mV 0mV G 700mV/525mV 300mV 0mV B 700mV/525mV 300mV 0mV Figure 127. ...
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SD OUTPUT PLOTS VOLTS IRE:FLT 100 0 –50 L76 MICROSECONDS APL = 44.5% PRECISION MODE OFF 525 LINE NTSC SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00V AT 6.72μs µ FRAMES ...
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ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 8–VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125: F ...
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ACTIVE VIDEO 622 623 624 625 Figure 139. ITU-R BT.1358 (625p) VERTICAL BLANKING INTERVAL 1 2 747 748 749 750 VERTICAL BLANKING INTERVAL FIELD 1 1124 1125 VERTICAL BLANKING INTERVAL FIELD 2 561 562 ...
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ADV7390/ADV7391/ADV7392/ADV7393 APPENDIX 9–CONFIGURATION SCRIPTS The scripts listed in the following pages can be used to configure the ADV739x for basic operation. Certain features are enabled by default. If required for a specific application, further features can be enabled. Table 58 ...
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Table 61. 8-Bit 525i YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 67. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x80 ...
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Table 73. 16-Bit 525i RGB In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x80 0x10 NTSC ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 79. 10-Bit 625i YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x11 PAL standard. SSAF luma filter enabled. 1.3 MHz ...
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Table 85. 16-Bit 625i YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x80 0x11 PAL ...
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ADV7390/ADV7391/ADV7392/ADV7393 ENHANCED DEFINITION Table 89. ED Configuration Scripts Input Format Input Data Width 525p 8-Bit DDR 525p 8-Bit DDR 525p 10-Bit DDR 525p 10-Bit DDR 525p 16-Bit SDR 525p 16-Bit SDR 525p 16-Bit SDR 525p 16-Bit SDR 625p 8-Bit DDR ...
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Table 96. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x1C ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 104. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 ...
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Table 107. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x10 HD-SDR input mode. 0x30 0x2C 720p @ 60 Hz/59.94 Hz. EAV/SAV syn- chronization. EIA-770.3 ...
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ADV7390/ADV7391/ADV7392/ADV7393 Table 117. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 ...
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OUTLINE DIMENSIONS 5.00 BSC SQ PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE 6.00 BSC SQ PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ADV7390/ADV7391/ADV7392/ADV7393 0.60 MAX 0.60 MAX 25 24 0.50 ...
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... ADV7390BCPZ-REEL 2 −40°C to +85°C 2 ADV7391BCPZ −40°C to +85°C 2 ADV7391BCPZ-REEL −40°C to +85°C 2 ADV7392BCPZ −40°C to +85°C 2 ADV7392BCPZ-REEL −40°C to +85°C 2 ADV7393BCPZ −40°C to +85°C 2 ADV7393BCPZ-REEL −40°C to +85° EVAL-ADV739xFEZ 2 EVAL-ADV7390EBZ EVAL-ADV7391EBZ 2 ...