AM29LV800BB90EI Advanced Micro Devices, AM29LV800BB90EI Datasheet
AM29LV800BB90EI
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AM29LV800BB90EI Summary of contents
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Am29LV800B 8 Megabit ( 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS Single power supply operation — 2.7 to 3.6 volt read and write operations for battery-powered applications Manufactured on 0.32 µm process ...
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GENERAL DESCRIPTION The Am29LV800B Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The device is also available in Known Good ...
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TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . ...
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PRODUCT SELECTOR GUIDE Family Part Number Speed Options Full Voltage Range: V Max access time ACC Max CE# access time Max OE# access time Note: See “AC Characteristics” for ...
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CONNECTION DIAGRAMS This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for more information. A15 1 A14 2 A13 3 A12 4 A11 5 6 A10 ...
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CONNECTION DIAGRAMS This device is also available in Known Good Die (KGD) form. Refer to publication number 21536 for more information. RY/BY# A18 A17 CE OE# DQ0 DQ8 DQ1 DQ9 ...
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Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. PIN CONFIGURATION A0–A18 = 19 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. Am29LV800B T - DEVICE NUMBER/DESCRIPTION Am29LV800B 8 Megabit ...
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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is composed of ...
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WE# and CE and OE For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte ...
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Output Disable Mode When the OE# input output from the device is IH disabled. The output pins are placed in the high imped- ance state. Table 2. Am29LV800BT Top Boot Block Sector Addresses Sector A18 A17 ...
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Table 3. Am29LV800BB Bottom Boot Block Sector Addresses Sector A18 A17 A16 A15 SA0 SA1 SA2 SA3 SA4 SA5 0 ...
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Table 4. Am29LV800B Autoselect Codes (High Voltage Method) Description Mode CE# Manufacturer ID: AMD L Device ID: Word L Am29LV800B Byte L (Top Boot Block) Device ID: Word L Am29LV800B Byte L (Bottom Boot Block) Sector Protection Verification L L ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 5 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or ...
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PROM programmers and requires V on address bit A9. The autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect com- mand. The device then enters the autoselect mode, and the system ...
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Write Program Command Sequence from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 5 for program command sequence. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a ...
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When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the sta- tus of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to ...
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Table 5. Am29LV800B Command Definitions Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte Word Sector ...
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WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 6 and the following subsections de- scribe the functions of these bits. DQ7, RY/BY#, and ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...
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The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, de- termining the ...
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Operation Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Reading within Erase Suspended Sector Erase Suspend Reading within Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . – +150 C Ambient Temperature with Power Applied ...
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DC CHARACTERISTICS CMOS Compatible Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I CC2 (Notes ...
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DC CHARACTERISTICS (Continued) Zero Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...
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TEST CONDITIONS Device Under Test C L 6.2 k Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Table 7. Test Specifications ...
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AC CHARACTERISTICS Read Operations Parameter JEDEC Std t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output Delay ...
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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded t READY Algorithms) to Read or Write (See Note) t RESET# ...
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AC CHARACTERISTICS Word/Byte Configuration (BYTE#) Parameter JEDEC Std t t CE# to BYTE# Switching Low or High ELFL/ ELFH t BYTE# Switching Low to Output HIGH Z FLQZ t BYTE# Switching High to Output Active FHQV CE# OE# BYTE# BYTE# ...
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AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data ...
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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# OE Data RY/BY VCS Notes program address program data Illustration shows device ...
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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data 55h RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid ...
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AC CHARACTERISTICS t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...
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AC CHARACTERISTICS Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Temporary Sector ...
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AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 µs CE# WE# OE# * For sector protect For sector unprotect ...
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AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH DS ...
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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Byte Mode Chip Programming Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following conditions 3.0 ...
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PHYSICAL DIMENSIONS* TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. 40 Am29LV800B Dwg rev AA; 10/99 ...
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PHYSICAL DIMENSIONS TSR048—48-Pin Reverse TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. Am29LV800B Dwg rev AA; 10/99 41 ...
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PHYSICAL DIMENSIONS FBB 048—48-Ball Fine-Pitch Ball Grid Array (FBGA Am29LV800B Dwg rev AF; 10/99 ...
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PHYSICAL DIMENSIONS SO 044—44-Pin Small Outline Package 43 Am29LV800B Dwg rev AC; 10/99 ...
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REVISION SUMMARY Revision E (January 1998) Distinctive Characteristics Changed typical read and program/erase current specifications. Device now has a guaranteed minimum endurance of 1,000,000 write cycles. In-System Sector Protect/Unprotect Algorithm Figure Corrected Changed wait specification to 150 ...
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... Trademarks Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...