CY7C65113 Cypress Semiconductor Corporation., CY7C65113 Datasheet
CY7C65113
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CY7C65113 Summary of contents
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... CY7C65013 CY7C65113 USB Hub with Microcontroller Cypress Semiconductor Corporation • 3901 North First Street • San Jose CY7C65013 CY7C65113 • CA 95134 • 408-943-2600 July 6, 2001 ...
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... Timer (MSB) ................................................................................................................................ CONFIGURATION REGISTER .............................................................................................. COMPATIBLE CONTROLLER ............................................................................................. 21 13.0 PROCESSOR STATUS AND CONTROL REGISTER ............................................................... 23 14.0 INTERRUPTS .............................................................................................................................. 24 14.1 Interrupt Vectors ........................................................................................................................ 24 14.2 Interrupt Latency ....................................................................................................................... 26 14.3 USB Bus Reset Interrupt ........................................................................................................... 26 14.4 Timer Interrupt ........................................................................................................................... 26 14.5 USB Endpoint Interrupts ........................................................................................................... 26 14.6 USB Hub Interrupt ..................................................................................................................... 26 14.7 GPIO Interrupt ............................................................................................................................ Interrupt ................................................................................................................................ 27 15.0 USB OVERVIEW ......................................................................................................................... 28 TABLE OF CONTENTS 2 CY7C65013 CY7C65113 ...
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... C Data Register 0x29 (separate read/write registers) ............................................. 22 2 Figure 12- Status and Control Register 0x28 (read/write) .................................................... 22 Figure 13-1. Processor Status and Control Register 0xFF ............................................................ 23 Figure 14-1. Global Interrupt Enable Register 0x20 (read/write) ................................................... 24 Figure 14-2. USB Endpoint Interrupt Enable Register 0x21 (read/write) ...................................... 24 LIST OF FIGURES 3 CY7C65013 CY7C65113 ...
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... Table 16-1. Control Bit Definition for Downstream Ports .............................................................. 30 Table 16-2. Control Bit Definition for Upstream Port ..................................................................... 33 Table 17-1. Memory Allocation for Endpoints ................................................................................ 34 Table 18-1. USB Register Mode Encoding ...................................................................................... 37 Table 18-2. Decode table for Table 18-3: “Details of Modes for Differing Traffic Conditions” ... 38 Table 18-3. Details of Modes for Differing Traffic Conditions ....................................................... 39 LIST OF TABLES 4 CY7C65013 CY7C65113 ...
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... Improved output drivers to reduce EMI • Operating voltage from 4.0V to 5.5V DC • Operating temperature from degrees Celsius • CY7C65013 available in 48-pin PDIP (-PC) or 48-pin SSOP (-PVC) packages • CY7C65113 available in 28-pin SOIC (-SC) or 28-pin PDIP (-PC) packages • Industry standard programmer support 5 CY7C65013 ...
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... Additionally, each I/O pin can be used to generate a GPIO interrupt to the microcontroller. All of the GPIO interrupts all share the same “GPIO” interrupt vector. The CY7C65113 has 11 GPIO pins (P0[7:0], P1[2:0]), both rated per pin (typical) sink current. Multiple GPIO pins can be connected together to drive a single output for more drive current capacity. ...
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... GPIO PORT 2 P2[3] GPIO High Current P3[1] Outputs PORT 3 P3[0] CY7C65013 only comp. SCLK SDATA Interface Compatible interface enabled by firmware through P2[1:0] or P1[1:0] 7 CY7C65013 CY7C65113 D+[0] Upstream USB Port D–[0] USB D+[1] D–[1] Transceiver USB D+[4] Transceiver D–[4] USB D+[5] Transceiver D–[5] USB D+[7] Transceiver D–[7] CY7C65013 only ...
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... REF 13 D–[5] 36 P0[ D+[5] P0[ GND 16 33 P2[ D–[ D+[ P2[ P0[ P0[ P0[ P0[6] 8 CY7C65013 CY7C65113 CY7C65113 P1[ P1[0] 4 P1[2] 25 D–[ D+[ D–[ D+[ GND P0[ P0[ P0[4] 14 ...
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... GPIO Port 0 Data 0x01 R/W GPIO Port 1 Data 0x02 R/W GPIO Port 2 Data 0x03 R/W GPIO Port 3 Data 0x04 W Interrupt Enable for Pins in Port 0 0x05 W Interrupt Enable for Pins in Port 1 0x06 W Interrupt Enable for Pins in Port 2 9 CY7C65013 CY7C65113 Function Page ...
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... Hub Downstream Ports SE0 Status 0x50 R Hub Downstream Ports Differential Data 0x51 R/W Hub Downstream Ports Force LOW (Ports [1:4]) 0x52 R/W Hub Downstream Ports Force HIGH (Ports [5:7]) 0xFF R/W Microprocessor Status and Control Register 10 CY7C65013 CY7C65113 Function Page ...
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... ASR 1D 5 RLC 1E RRC 1F 4 RET RETI 50- 80-8F 5 JNC 90-9F 10 JACC A0-AF 5 INDEX B0- CY7C65013 CY7C65113 operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 address ...
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... CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack during a RETI instruction. Only the program counter is restored during a RET instruction. The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up. 12 CY7C65013 CY7C65113 ...
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... USB address A endpoint 2 interrupt vector 0x000E USB address B endpoint 0 interrupt vector 0x0010 USB address B endpoint 1 interrupt vector 0x0012 Hub interrupt vector 0x0014 Reserved 0x0016 GPIO interrupt vector 2 0x0018 I C interrupt vector 0x001A Program Memory begins here 0x1FDF 8 KB (-32) PROM ends here (CY7C65013, CY7C65113) 13 CY7C65013 CY7C65113 ...
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... Refer to Section 5.5 for a description of DSP . 2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Table 17-1. Address 0x00 Program Stack Growth user selected User variables USB FIFO space for up to two Addresses and five endpoints 0xFF 14 CY7C65013 CY7C65113 Data Stack Growth [2] ...
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... Move 20 hex into Accumulator (must be D8h or less) SWAP A,DSP ; swap accumulator value into DSP register 5.6 Address Modes The CY7C65013 and CY7C65113 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. 5.6.1 Data (Immediate) “Data” address mode refers to a data operand that is actually a constant encoded in the instruction example, consider the instruction that loads A with the constant 0xD8: • ...
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... XTALIN (pin Figure 6-1. Clock Oscillator On-Chip Circuit to stabilize at a valid operating voltage before the chip executes code. CC drops below approximately 2.5V, and remains asserted until CY7C65013 CY7C65113 to internal PLL has risen above approximately CC rises above this level CC level is CC ...
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... Write to Status and Control Register - Enter suspend, wait for USB activity (or GPIO Interrupt) nop ; This executes before any ISR ... ; Remaining code for exiting suspend routine WATCH No write to WDT Execution begins at register, so WDR Reset Vector 0x0000 goes HIGH Figure 7-1. Watch Dog Reset (WDR) 17 CY7C65013 CY7C65113 WATCH or Gnd. Note: CC ...
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... Figure 9-1. Block Diagram of a GPIO Pin P0[4] P0[3] Figure 9-2. Port 0 Data 0x00 (read/write P1[4] P1[3] Figure 9-3. Port 1 Data 0x01 (read/write P2[4] P2[3] Figure 9-4. Port 2 Data 0x02 (read/write P3[4] P3[3] Figure 9-5. Port 3 Data 0x03 (read/write) 18 CY7C65013 CY7C65113 CC Q2 GPIO PIN sink sink 2 1 P0[2] P0[ P1[2] P1[ P2[2] P2[ P3[2] P3[1] 0 P0[0] 0 P1[0] ...
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... Specifications ‘1’ is written to the unused data bit and the port is configured with open drain outputs, the unused data bit remains in an indeterminate state. Therefore unused port bit is programmed in open-drain mode, it must be written with a ‘0.’ Notice that the CY7C65113 always requires that P1[7:3], P2[7:0], and P3[7:0] be written with a ‘0.’ When the CY7C65013 is used, the P1[3], P2[2:0], and P3[7:2] should be written with a ‘0.’ ...
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... P1[4] P1[ P2[4] P2[ P3[4] P3[ Timer Timer Bit 5 Bit 4 Bit 3 Figure 10-1. Timer Register 0x24 (read only Reserved Timer Bit 11 Figure 10-2. Timer Register 0x25 (read only) 20 CY7C65013 CY7C65113 P0[2] P0[1] P0[ P1[2] P1[1] P1[ P2[2] P2[1] P2[ P3[2] P3[1] P3[ Timer Timer Timer Bit 2 Bit 1 ...
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... C Data Register (Figure 12-1) and interrupt, as all bits are valid at that time. Polling this register at other times could 2 C compatible pins. Once the I C compatible functionality is enabled by setting bit 0 of the 21 CY7C65013 CY7C65113 1.024-ms Interrupt 128- s Interrupt 1 0 1-MHz Clock D1 D0 ...
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... Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration. Clearing from generates Stop bit compatible block to initiate a master mode transaction by sending a start bit and 2 C Stop bit is generated. 22 CY7C65013 CY7C65113 2 C compatible interface is the same as that ...
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... C compatible mode, the two pins operate in open drain mode, independent R/W R/W R/W Power-On Suspend Reset 23 CY7C65013 CY7C65113 2 C address packet compatible bus at the ACK bit time start or restart target address for the restart must be written 2 C compatible bus, e. compatible pins. When this bit is ...
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... C compatible operation, the internal USB hub various USB R/W R/W Reserved USB Hub Interrupt Enable R/W R/W EPB1 EPB0 Interrupt Interrupt Enable Enable 2 C interrupt) has the lowest priority. Although Reset is not 24 CY7C65013 CY7C65113 R/W R/W R/W 1.024-ms 128- s USB Bus RST Interrupt Interrupt Interrupt Enable Enable Enable R/W R/W R/W EPA2 EPA1 EPA0 ...
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... USB Address B Endpoint 0 interrupt 0x0010 USB Address B Endpoint 1 interrupt 0x0012 USB Hub interrupt 0x0014 DAC interrupt 0x0016 GPIO interrupt 2 0x0018 I C interrupt 25 CY7C65013 CY7C65113 To CPU CPU IRQ Sense IRQ Global Int Enable Interrupt Sense Enable Bit Controlled by DI, EI, and CLR RETI Instructions Interrupt ...
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... Enable Register (Figure 16-3). The connect/disconnect event on a port does not generate an interrupt if the SIE does not drive the port (i.e., the port is being forced Interrupt Interrupt Vector Bit 4 Vector Bit 3 26 CY7C65013 CY7C65113 Interrupt Interrupt Reads ‘0’ Vector Bit 2 Vector Bit 1 ...
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... Disable Enable (Bit 5, Register 0x20) Figure 14-5. GPIO Interrupt Structure 2 C compatible bus to signal the need for firmware interaction. This generally 2 C compatible hardware in the idle state. 27 CY7C65013 CY7C65113 GPIO Interrupt Flip Flop Interrupt D Q Priority Encoder CLR 2 C registers. Refer to Section 12.0 for details on ...
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... USB address (for example, Address A interrupt occurs. 28 CY7C65013 CY7C65113 2 C register contents may be must be ext ...
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... USB traffic can flow to and from that port Port 5 Port 4 Connect Connect Status Status Port 5 Port 4 Speed Speed 29 CY7C65013 CY7C65113 resistors from each signal line to UDN to indicate full speed USB device. REG Port 3 Port 2 Port 1 Connect Connect Connect Status Status Status 2 1 ...
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... SE0 on all downstream ports when unconfigured, as required in the USB 1.1 specification Port 5 Port 4 Enable Enable may cause current flow into the pin Port 3 Port 2 Control Bit 0 Control Bit 1 30 CY7C65013 CY7C65113 2 1 Port 3 Port 2 Port 1 Enable Enable Enable 2 1 Port 2 Port 1 Port 1 Control Bit 0 Control Bit 1 Control Bit 0 0 ...
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... SE0 Status Port 5 Port 4 Diff. Data Diff. Data Port 5 Port 4 Selective Selective Suspend Suspend 31 CY7C65013 CY7C65113 Force Low Force Low Force Low DD2 D– DD1 D+ DD1 D– Force High Force High Force High DD6 D– DD5 D+ DD5 D– ...
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... The three control bits allow the upstream port to be driven manually by firmware. For normal USB operation, all of these bits must be cleared. Table 16-2 shows how the control bits affect the upstream port Resume 5 Resume R/C D+ D– Bus Activity Upstream 32 CY7C65013 CY7C65113 Resume 3 Resume 2 Resume R/W R/W R/W Control Control Control Bit 2 Bit 1 Bit 0 ...
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... Bit 7 controls the size of the endpoints and bit 6 controls the number of addresses. These configuration options are detailed in Table 17-1. Endpoint FIFOs are part of user RAM (as shown in Section 5.4.1 Device Device Address Address Bit 5 Bit 4 Bit 3 33 CY7C65013 CY7C65113 Device Device Device Address Address Address Bit 2 Bit 1 Bit 0 ...
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... Address 0xA8 8 EPA4 0xB0 8 EPA3 0xB8 8 EPA2 0xC0 32 EPA1 0xE0 32 EPA0 ACK Mode Bit 3 34 CY7C65013 CY7C65113 One USB address (A Reg 0x1F,Bits [7,6] = [1,1] Start Start Size Label Address 0xD8 8 EPA3 0xA8 0xE0 8 EPA4 0xB0 0xE8 8 EPA0 0xB8 0xF0 8 EPA1 0xC0 ...
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... SIE might have made since the previous IO read of that register ACK Mode Bit Byte Count Byte Count Bit 5 Bit 4 Bit 3 35 CY7C65013 CY7C65113 Mode Mode Mode Bit 2 Bit 1 Bit Byte Count Byte Count Byte Count Bit 2 Bit 1 ...
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... Data Packet update data Data Packet update only if FIFO is update only if FIFO is Written (see Table 18-3) Written (see Table 20-3) 36 CY7C65013 CY7C65113 H/S Pkt update ACK NAK STALL C H/S Pkt ...
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... This mode is changed by SIE on issuance of ACK --> 1010 NAK ignore An ACK from mode 1101 --> 1100 TX cnt ignore This mode is changed by SIE on issuance of ACK --> 1100 stall ignore NAK check An ACK from mode 1111 --> 111 Ack In - Status Out TX cnt check This mode is changed by SIE on issuance of ACK -->1110 37 CY7C65013 CY7C65113 ...
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... Status bits PID Status bits dval DTOG DVAL COUNT Setup The validity of the received data TX: transmit TX0: transmit 0-length packet RX: receive 38 CY7C65013 CY7C65113 What the SIE does to Mode bits Interrupt? End Point Mode In Out ACK Response Acknowledge phase completed Int ...
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... UC UC invalid valid 1 1 updates UC valid 0 1 updates UC valid updates 1 updates UC 39 CY7C65013 CY7C65113 Set End Point Mode In Out ACK response ACK NoChange ignore NoChange ignore NoChange ignore ...
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... CY7C65013 CY7C65113 Set End Point Mode In Out ACK response NoChange ignore NoChange ignore Stall ACK NoChange ...
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... MHz 0V 0V Vref OUT 2.2 uF . 22x8(R ext D0- ) D1- D0+ D1+ D2- XTALO D2+ D3- XTALI D3+ GND GND D4- Vpp D4+ 15K(x8 UDN POWER MANAGEMENT 41 CY7C65013 CY7C65113 ) 0V USB-A Vbus D- D+ GND 0V USB-A Vbus D- D+ GND 0V USB-A Vbus D- D+ GND 0V USB-A Vbus D- D+ GND 0V ...
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... CC 42 CY7C65013 CY7C65113 Unit Conditions V 3.3V ± GPIO source current A [ USB Traffic A Any pin V | (D+)–(D– < V < 3. series with each USB pin k 1.5 k ±5 ...
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... Figure 22-2. USB Data Signal Timing Package Name Package Type O48 48-Pin (300-Mil) SSOP S21 28-Pin SOIC P25 48-Pin (600 Mil) PDIP P21 28-Pin (300-Mil) PDIP 43 CY7C65013 CY7C65113 Min. Max. 6 ±0.25% 166.25 167.08 0.45 t CYC 0.45 t CYC 111 12 ±0.25% 8.192 14 ...
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... Package Diagrams 48-Lead Shrunk Small Outline Package O48 28-Lead (300-Mil) Molded DIP P21 44 CY7C65013 CY7C65113 51-85061-B 51-85014-B ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 48-Lead (600-Mil) Molded DIP P25 28-Lead (300-Mil) Molded SOIC S21 CY7C65013 CY7C65113 51-85020-A 51-85026-A ...