ICS874001AGI-02 Integrated Device Technology, Inc., ICS874001AGI-02 Datasheet

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ICS874001AGI-02

Manufacturer Part Number
ICS874001AGI-02
Description
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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ICS874001AGI-02LF
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IDT
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ICS874001AGI-02LF
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IDT
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PCI EXPRESS/JITTER ATTENUATOR
G
attenuator may be required to attenuate high frequency random
and deterministic jitter components from the PLL synthesizer
and from the system board. The ICS874001I-02 has 2 PLL
bandwidth modes: 2.2MHz and 3MHz. The 2.2MHz mode will
provide maximum jitter attenuation, but with higher PLL tracking
skew and spread spectrum modulation from the motherboard
synthesizer may be attenuated. The 3MHz bandwidth provides
the best track-ing skew and will pass most spread profiles, but
the jitter attenuation will not be as good as the lower bandwidth
modes. The 874001I-02 can be set for different modes using the
F_SELx pins, as shown in Table 3C.
The ICS874001I-02 uses IDT’s 3
PLL technology to achive the lowest possible phase noise.
The device is packaged in a small 20-pin TSSOP package,
making it ideal for use in space constrained applications such as
PCI Express add-in cards.
PLL B
B
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
F_SEL[1:0]
BW_SEL
0 = PLL Bandwidth: 2.2MHz (default)
1 = PLL Bandwidth: 3MHz
HiPerClockS™
PLL_SEL
BW_SEL
0 = 2.2MHz
1 = 3MHz
IC S
LOCK
ENERAL
nCLK
/ ICS
CLK
MR
OE
ANDWIDTH
Pullup
Pulldown
Pulldown
Pullup
Pullup/Pulldown
Pulldown
Pullup
PCI EXPRESS/JITTER ATTENUATOR
D
The ICS874001I-02 is a high performance Jitter
Attenuator designed for use in PCI Express™ sys-
tems. In some PCI Express systems, such as those
found in desktop PCs, the PCI Express clocks are
generated from a low bandwidth, high phase noise
PLL frequency synthesizer. In these systems, a jitter
IAGRAM
D
C
ESCRIPTION
ONTROL
2
T
ABLE
Detector
Phase
rd
Generation FemtoClock
Internal Feedback
PLL _SEL C
0 = Bypass
1 = VCO (default)
490 - 640MHz
÷5
VCO
ONTROL
TM
T
1
ABLE
F
P
One differential LVDS output pair
One differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 640MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 50ps (maximum) design target
3.3V or 2.5V operating supply
Two bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
EATURES
IN
0
1
A
SSIGNMENT
Output Divider
0 0 ÷5
0 1 ÷4
1 0 ÷2 (default)
1 1 ÷1
6.5mm x 4.4mm x 0.92mm package body
ICS874001AGI-02 REV. A JANUARY 3, 2007
PLL_SEL
BW_SEL
F_SEL1
F_SEL0
V
ICS874001I-02
V
MR
20-Lead TSSOP
DDA
nc
nc
nc
DD
G Package
Top View
ICS874001I-02
1
2
3
4
5
6
7
8
9
10
PRELIMINARY
20
19
18
17
16
15
14
13
12
11
Q
nQ
nc
V
Q
nQ
nc
nc
GND
nCLK
CLK
OE
DDO

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ICS874001AGI-02 Summary of contents

Page 1

... BW_SEL 6 15 F_SEL1 7 14 GND V 13 nCLK 8 DDA F_SEL0 CLK ICS874001I-02 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View Output Divider ÷ ÷ ÷2 (default ÷1 ICS874001AGI-02 REV. A JANUARY 3, 2007 ...

Page 2

... ICS874001AGI-02 REV. A JANUARY 3, 2007 PRELIMINARY ...

Page 3

... ICS874001AGI-02 REV. A JANUARY 3, 2007 µ A µ ...

Page 4

... ICS874001AGI-02 REV. A JANUARY 3, 2007 PRELIMINARY µ A µ A µ A µ ...

Page 5

... Cycles -C J YCLE ITTER PERIOD t PW odc = x 100% t PERIOD UTY YCLE ULSE IDTH ERIOD V DD out LVDS out ➤ OLTAGE ETUP ICS874001AGI-02 REV. A JANUARY 3, 2007 PRELIMINARY SCOPE Qx nQx ➤ ➤ ...

Page 6

... V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input V_REF C1 0. INGLE NDED IGNAL RIVING 6 PRELIMINARY 3.3V DDA . IGURE OWER UPPLY ILTERING CLK nCLK D I IFFERENTIAL NPUT ICS874001AGI-02 REV. A JANUARY 3, 2007 = DD ...

Page 7

... LVPECL Input 3B CLK/ CLK LOCK N NPUT 3.3V LVPECL D RIVER Ohm LVDS_Driv er R1 100 Ohm 3D CLK/ CLK LOCK N NPUT 3.3V LVDS D RIVER ICS874001AGI-02 REV. A JANUARY 3, 2007 PRELIMINARY D RIVEN BY 3.3V CLK nCLK Receiv er D RIVEN BY ...

Page 8

... PCI EXPRESS/JITTER ATTENUATOR the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used recommended to terminate the across near unused outputs. LVDS R1 100 100 Differential Transmission LVDS D IGURE YPICAL RIVER 8 PRELIMINARY 3. ERMINATION ICS874001AGI-02 REV. A JANUARY 3, 2007 ...

Page 9

... DDA_MAX = 3.465V * 20mA = 69.3mW DDO_MAX TM * Pd_total + 20-L TSSOP EAD ORCED ONVECTION by Velocity (Linear Feet per Minute 114.5°C/W 73.2°C/W 9 PRELIMINARY devices is 125°C. must be used. Assuming a JA 200 500 98.0°C/W 88.0°C/W 66.6°C/W 63.5°C/W ICS874001AGI-02 REV. A JANUARY 3, 2007 ...

Page 10

... RANSISTOR OUNT The transistor count for ICS874001I-02 is: 1608 IDT ™ / ICS ™ PCI EXPRESS/JITTER ATTENUATOR R I ELIABILITY NFORMATION 20 L TSSOP EAD by Velocity (Linear Feet per Minute 114.5°C/W 73.2°C/W 10 PRELIMINARY 200 500 98.0°C/W 88.0°C/W 66.6°C/W 63.5°C/W ICS874001AGI-02 REV. A JANUARY 3, 2007 ...

Page 11

... ° Reference Document: JEDEC Publication 95, MO-153 11 PRELIMINARY ° ICS874001AGI-02 REV. A JANUARY 3, 2007 ...

Page 12

... ICS874001AGI-02 REV. A JANUARY 3, 2007 ° ° ° ° ...

Page 13

... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners ...

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