MT46H32M16LFBF-6 Micron Semiconductor Products, MT46H32M16LFBF-6 Datasheet
MT46H32M16LFBF-6
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MT46H32M16LFBF-6 Summary of contents
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Mobile DDR SDRAM MT46H32M16LF – 8 Meg banks MT46H16M32LF – 4 Meg banks Features • 1.70–1.95V DD/ DD • Bidirectional data strobe per byte of data (DQS) • ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 512Mb Mobile DDR Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1: Key Timing Parameters ( ...
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Figure 1: 512Mb Mobile DDR Part Numbering Micron Technology Product Family 46 = Mobile DDR SDRAM Operating Voltage H = 1.8V/1.8V Configuration 32 Meg Meg x 32 Addressing LF = Mobile standard addressing LG = Reduced page-size ...
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Functional Block Diagrams Figure 2: Functional Block Diagram (32 Meg x 16) CKE CK# CK CS# Control logic WE# CAS# Refresh RAS# counter Standard mode register Extended mode register address Address address BA0, BA1 register PDF: 09005aef82d5d305/Source: 09005aef82d5d2e7 512mb_ddr_mobile_sdram_t47m_density__2.fm - ...
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Figure 3: Functional Block Diagram (16 Meg x 32) CKE CK# CK Control CS# logic WE# CAS# RAS# Refresh counter Standard mode register Extended mode register address Address, Address BA0, BA1 register PDF: 09005aef82d5d305/Source: 09005aef82d5d2e7 512mb_ddr_mobile_sdram_t47m_density__2.fm - Rev. D 05/08 ...
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Ball Assignments and Descriptions Figure 4: 60-Ball VFBGA Assignments – 8mm x 9mm (Top View Notes test pin that must be tied to V PDF: 09005aef82d5d305/Source: ...
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Figure 5: 90-Ball VFBGA Ball Assignments – 10mm x 13mm (Top View Notes test pin that must be tied to V ...
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Table 1: VFBGA Ball Descriptions 60-Ball VFBGA 90-Ball VFBGA G2 G9, G8, G7 G9, G8, G7 F2, F8 K8, K2, F8, F2 H8, H9 H8, H9 J8, J9, K7, K8, K2, J8, J9, ...
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Table 1: VFBGA Ball Descriptions (continued) 60-Ball VFBGA 90-Ball VFBGA E8, E2 L8, L2, E8, E2 A7, B1, C9, D1, E9 A7, B1, C9, D1, E9, L9, M1, N9, P1, R7 A3, B9, C1, E1 A3, B9, C1, E1, L1, ...
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Package Dimensions Figure 6: 60-Ball VFBGA Package Seating plane A 0.1 A 60x Ø0.45 Dimensions apply to solder balls post-reflow. The pre-reflow balls are Ø0.42 on Ø0.4 SMD ball pads. 3.6 7.2 0.8 TYP 0.8 TYP Notes: ...
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Figure 7: 90-Ball VFBGA Package Seating plane A 0.1 A 90X Ø0.45 Dimensions apply to solder balls post-reflow. The pre-reflow balls are Ø0.42 on Ø0 SMD ball pads. 5.6 11.2 0.8 TYP 3.2 Notes: 1. All dimensions ...
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Electrical Specifications Stresses greater than those listed in Table 4 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
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Table 3: AC/DC Electrical Characteristics and Operating Conditions (continued) Notes: 1–5 apply to all parameters/conditions in this table; V Parameter/Condition Output leakage current (DQs are disabled; 0V ≤ V ≤ V OUT Operating temperature Commercial Industrial Notes: 1. All voltages ...
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Table 4: Capacitance (x16, x32) Note 1 applies to all the parameters in this table. Parameter Input capacitance: CK, CK# Delta input capacitance: CK, CK# Input capacitance: command and address Delta input capacitance: command and address Input/output capacitance: DQs, DQS, ...
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Table 5: I Specifications and Conditions (x16) DD Notes: 1–5 apply to all parameters/conditions in this table; notes appear on page 19; V Parameter/Condition Operating 1 bank active-precharge current (MIN (MIN); CKE is HIGH; CS ...
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Table 6: I Specifications and Conditions (x32) DD Notes: 1–5 apply to all parameters/conditions in this table; notes appear on page 19; V Parameter/Condition Operating 1 bank active-precharge current (MIN ...
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Table Specifications and Conditions DD Notes: 1–5, 7, and 12 apply to all parameters/conditions in this table; V Parameter/Condition Self refresh t t CKE = LOW (MIN); Address and control inputs are stable; Data ...
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Figure 8: Typical I 6 Curves DD 700 650 600 550 500 450 400 350 300 250 200 150 100 -40 -35 -30 -25 -20 -15 -10 -5 Table 8: Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–9 apply ...
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Table 8: Electrical Characteristics and Recommended AC Operating Conditions (continued) Notes: 1–9 apply to all parameters in this table; V Parameter DQS input high pulse width DQS input low pulse width DQS–DQ skew, DQS to last DQ valid, per group, ...
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Table 8: Electrical Characteristics and Recommended AC Operating Conditions (continued) Notes: 1–9 apply to all parameters in this table; V Parameter SRR-to-READ DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE-to-READ command delay ...
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Referenced to each output group: for x16, LDQS with DQ0–DQ7; and UDQS with DQ8– DQ15. For x32, DQS0 with DQ0–DQ7; DQS1 with DQ8–DQ15; DQS2 with DQ16–DQ23; and DQS3 with DQ24–DQ31. 13. DQ and DM input slew rates must not ...
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Table 9: Target Output Drive Characteristics (Full Strength) Notes 1–2 apply to all values. Characteristics are specified under best and worst process variations/conditions. Voltage (V) 0.00 0.10 0.20 0.30 0.40 11.20 0.50 14.00 0.60 16.80 0.70 19.60 0.80 22.40 0.85 ...
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Table 10: Target Output Drive Characteristics (Three-Quarter Strength) Notes 1–2 apply to all values. Characteristics are specified under best and worst process variations/conditions. Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 11.76 0.70 13.72 0.80 15.68 0.85 16.66 0.90 ...
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Table 11: Target Output Drive Characteristics (One-Half Strength) Notes 1–3 apply to all values. Characteristics are specified under best and worst process variations/conditions. Voltage (V) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 10.16 0.85 10.80 0.90 10.80 0.95 ...
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Functional Description The Mobile DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the ...
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Commands Table 14 and Table 15 provide a quick reference of available commands. This is followed by a written description of each command. Three additional truth tables (Table 16 on page 34, Table 17 on page 35, and Table 18 ...
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DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the Mobile DDR SDRAM. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected Mobile DDR ...
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READ The READ command is used to initiate a burst read access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided on inputs A0–Ai (where i = the most significant column ...
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LOW, the corresponding data will be written to memory; if the DM signal is regis- tered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location WRITE or ...
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Figure 4: PRECHARGE Command RAS# CAS# WE# Address BA0, BA1 Notes A10 is HIGH, bank address becomes “Don’t Care.” BURST TERMINATE The BURST TERMINATE command is used to truncate READ bursts with auto precharge disabled. The most recently ...
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SELF REFRESH The SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the Mobile DDR SDRAM retains data without ...
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Operations Table 3: Truth Table – Current State Bank n – Command to Bank n Notes: 1–6; notes appear below and on next page Current State CS# RAS# Any Idle ...
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The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Accessing mode register: Precharging all: 6. All states and sequences not shown ...
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Notes: 1. This table applies when CKE the previous state was self refresh), after down full initialization if the previous state was deep power-down). 2. This table describes alternate bank operation, except where noted (for example, the cur- ...
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Table 5: Truth Table – CKE Notes: 1–4 CKE CKE Current State Active power-down L L Deep power-down L L (Precharge) power-down L L Self refresh L H Active power-down L H Deep power-down ...
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Figure 6: Mobile DRAM Simplified State Diagram Power Power on applied PRE PREALL LMR LMR EMR WRITE WRITE A PRE ACT = ACTIVE AREF = AUTO REFRESH BST = BURST TERMINATE CKEH = Exit power-down CKEL = Enter power-down DPD ...
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Initialization The following sections provide detailed information covering device initialization, register definition, and device operation. Prior to normal operation, Mobile DDR SDRAMs must be powered up and initialized in a predefined manner. Initialization procedures, other than those specified, will result ...
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Figure 7: Initialize and Load Mode Registers ( ( ) ) CK LVCMOS HIGH LEVEL ( ( ) ) CKE ( ( ...
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Register Definition Mode Registers The mode registers are used to define the specific mode of operation of the Mobile DDR SDRAM. Two mode registers are used to specify the operational characteristics of the device: standard mode register and extended mode ...
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Burst Length (BL) Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length (BL) being programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ ...
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Table 6: Burst Definition Table Burst Length Starting Column Address ...
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CAS Latency (CL) The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first output data. The latency can be set clocks, as shown in ...
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Temperature-Compensated Self Refresh (TCSR) On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator. Programming of the TCSR bits will have no effect on the device. The self refresh ...
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Figure 10: Extended Mode Register BA1 n Mode Register Definition Status register 1 0 Extended mode register 1 1 Reserved En ... E10 ...
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Figure 11: SRR Timing Command PRE NOP t RP Address BA0, BA1 DQS DQ Notes: 1. All banks must be idle prior to status register read. 2. NOP or DESELECT commands are required between LMR ...
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Figure 12: Status Register Definition DQ31..DQ16 DQ15 DQ14 DQ13 S31..S16 S15 S14 S13 31.. Reserved Density S15 S14 S13 Density 128Mb 256Mb 1 0 512Mb 1Gb ...
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A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by ...
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READ command, where x equals the number of desired data element pairs. This is shown in Figure 27 on page 56. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until time is hidden ...
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Figure 14: Consecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes OUT (if 4, ...
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Figure 15: Nonconsecutive READ Bursts T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes OUT (if burst ...
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Figure 16: Random READ Accesses T0 CK# CK Command READ Bank, Address Col n DQS DQ T0 CK# CK Command READ Bank, Address Col n DQS DQ Notes OUT (if ...
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Figure 17: Terminating a READ Burst T0 CK# CK Command READ Bank a , Address Col n DQS DQ T0 CK# CK Command READ Bank a , Address Col n DQS DQ Notes: 1. Dout n = data-out from column ...
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Figure 18: READ-to-WRITE T0 CK# CK Command READ Bank, Address Col n DQS CK# CK Command READ Bank, Address Col n DQS DQ DM Notes OUT the ...
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Figure 19: READ-to-PRECHARGE T0 CK# CK Command READ Bank a, Address Col n DQS DQ T0 CK# CK Command READ Bank a, Address Col n DQS DQ Notes OUT interrupted burst of ...
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Figure 20: Data Output Timing – CK LDQS DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ (First data no longer valid) DQ0–DQ7 and LDQS, collectively ...
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Figure 21: Data Output Timing – DQS0/DQS1/DQS2/DQS3 2 DQ (Last data valid (First data no longer valid) DQ (Last data valid) DQ ...
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Figure 22: Data Output Timing – CK# CK NOP 4 Command READ 1 DQS or LDQS/UDQS 2 All DQ values, collectively Notes transitioning after DQS transitions define 2. All DQ must transition ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 11 on page 31. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. ...
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Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figure 41 on page 69 and Figure 42 on page 70. Note that only the data-in pairs that are registered prior to the subsequent ...
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Figure 24: Write – DM Operation CKE NOP 6 Command ACTIVE Row Address A10 Row BA0, BA1 Bank ...
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Figure 25: WRITE Burst Command Address t DQSS (NOM) DQS t DQSS (MIN) DQS t DQSS (MAX) DQS Notes uninterrupted burst shown. 3. A10 is LOW with the WRITE command (auto precharge ...
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Figure 27: Nonconsecutive WRITE-to-WRITE CK# Command Address DQS DQ DM Notes uninterrupted burst shown. 3. Each WRITE command may be to any bank. Figure 28: Random WRITE Cycles CK# Command Address DQS ...
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Figure 29: WRITE-to-READ – Uninterrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
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Figure 30: WRITE-to-READ – Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM Notes: ...
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Figure 31: WRITE-to-READ – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS ...
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Figure 32: WRITE-to-PRECHARGE – Uninterrupting T0 CK# CK Command WRITE Bank a , Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS DQ DM ...
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Figure 33: WRITE-to-PRECHARGE – Interrupting T0 CK# CK Command WRITE Bank a, Address Col DQSS (NOM) DQSS DQS DQSS (MIN) DQSS DQS DQSS (MAX) DQSS DQS ...
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Figure 34: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting T0 CK# CK Command WRITE Bank a, Address Col b t DQSS t DQSS (NOM) DQS DQSS t DQSS (MIN) DQS DQSS t DQSS (MAX) ...
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PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time ( mines whether one or ...
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Figure 35: Bank Read – with Auto Precharge CKE Command NOP ACTIVE Address Row A10 Row BA0, BA1 ...
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Figure 36: Bank Read – Without Auto Precharge CKE Command 6 ACTIVE NOP t IS Row Address A10 Row BA0, BA1 Bank x DM ...
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Figure 37: Bank Write – with Auto Precharge CKE NOP 4 Command ACTIVE Address Row A10 Row BA0, ...
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Figure 38: Bank Write – Without Auto Precharge CKE Command 6 ACTIVE NOP Address Row A10 Row ...
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Auto Refresh Auto refresh mode is used during normal operation of the Mobile DDR SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs. The AUTO REFRESH command is nonpersistent and must be issued each time a refresh is ...
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Self Refresh The self refresh mode can be used to retain data in the Mobile DDR SDRAM even if the rest of the system is powered down. When in the self refresh mode, the Mobile DDR SDRAM retains data without ...
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Power-Down Power-down (Figure 49 on page 78) is entered when CKE is registered LOW. If power- down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active ...
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Figure 42: Power-Down Mode (Active or Precharge CKE Command 1 Valid Address Valid DQS READ/WRITE access in progress power-down Notes: ...
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Figure 43: Deep Power-Down T0 CK# CK CKE Command NOP All banks idle with no activity on the data bus Notes: 1. Clock must be stable prior to CKE going HIGH. 2. DPD = deep power-down. 3. Upon exit of ...
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Figure 44: Clock Stop Mode CK# CK CKE Command Address DQ, DQS Exit clock stop mode Notes: 1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before any valid command. ...
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Revision History 512Mb: x16, x32 Mobile DDR SDRAM Rev. C, Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Revision History Commands, Operations, and Timing Diagrams Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...