MT48LC32M16A2TG Micron Semiconductor Products, MT48LC32M16A2TG Datasheet
MT48LC32M16A2TG
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MT48LC32M16A2TG Summary of contents
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... ARCHITECTURE MT48LC128M4A2TG 128 Meg x 4 MT48LC64M8A2TG 64 Meg x 8 MT48LC32M16A2TG 32 Meg x 16 512Mb: x4, x8, x16 SDRAM 512MSDRAM_D.p65 – Rev. D; Pub 1/02 ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. ...
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GENERAL DESCRIPTION The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits internally configured as a quad-bank DRAM with a syn- chronous interface (all signals are registered on the posi- tive edge of the clock ...
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TABLE OF CONTENTS Functional Block Diagram – 128 Meg x 4 .................... Functional Block Diagram – 64 Meg x 8 ................... Functional Block Diagram – 32 Meg x 16 ................. Pin Descriptions ........................................................... Functional Description ............................................... Initialization ............................................................ Register Definition ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH MODE REGISTER COUNTER 12 13 A0-A12, ADDRESS 15 BA0, BA1 REGISTER 12 512Mb: x4, x8, x16 SDRAM 512MSDRAM_D.p65 – Rev. D; Pub 1/02 FUNCTIONAL BLOCK DIAGRAM 128 Meg x 4 SDRAM ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 13 A0-A12, ADDRESS 15 BA0, BA1 REGISTER 11 512Mb: x4, x8, x16 SDRAM 512MSDRAM_D.p65 – Rev. D; Pub 1/02 FUNCTIONAL BLOCK DIAGRAM 64 Meg x 8 SDRAM ...
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CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# REFRESH COUNTER MODE REGISTER 12 13 A0-A12, ADDRESS 15 BA0, BA1 REGISTER 10 512Mb: x4, x8, x16 SDRAM 512MSDRAM_D.p65 – Rev. D; Pub 1/02 FUNCTIONAL BLOCK DIAGRAM 32 Meg x 16 SDRAM ...
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PIN DESCRIPTIONS PIN NUMBERS SYMBOL 38 CLK 37 CKE 19 CS# 18, 17, 16 RAS#, CAS#, WE# 39 x4, x8: DQM 15, 39 x16: DQML, DQMH 20, 21 BA0, BA1 23-26, 29-34, 22, 35, 36 A0–A12 ...
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FUNCTIONAL DESCRIPTION In general, the 512Mb SDRAMs (32 Meg banks, 16 Meg banks, and 8 Meg banks) are quad- bank DRAMs that operate at 3.3V and include a ...
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Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by ...
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CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks ...
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COMMANDS Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear TRUTH TABLE 1 – COMMANDS AND DQM OPERATION (Note: 1) NAME (FUNCTION) COMMAND INHIBIT ...
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COMMAND INHIBIT The COMMAND INHIBIT function prevents new com- mands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effec- tively deselected. Operations already in progress are not affected. NO OPERATION (NOP) ...
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BURST TERMINATE The BURST TERMINATE command is used to trun- cate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of ...
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Operation BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE com- mand, which selects both the bank and ...
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READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto ...
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The 512Mb SDRAM uses a pipelined architecture and therefore does not require the ...
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T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency = 2 T0 CLK COMMAND READ BANK, ADDRESS COL n DQ NOTE: Each READ command may be to any bank. DQM is LOW. 512Mb: x4, x8, x16 SDRAM 512MSDRAM_D.p65 ...
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Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed- length READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may ...
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A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. ...
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The disadvantage of the PRECHARGE command is that it requires that the com- mand and address buses be available at the appropriate time to issue the command; the ...
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WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge ...
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Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, ...
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PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Fixed-length or full-page WRITE bursts can be trun- cated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coinci- dent with ...
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CLOCK SUSPEND The clock suspend mode occurs when a column ac- cess/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deacti- vated, “freezing” the synchronous logic. For each positive clock edge ...
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CONCURRENT AUTO PRECHARGE An access command to (READ or WRITE) another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. ...
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WRITE with auto precharge 3. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank t ...
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TRUTH TABLE 2 – CKE (Notes: 1-4) CKE CKE CURRENT STATE n Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle Reading or Writing H H ...
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TRUTH TABLE 3 – CURRENT STATE BANK n - COMMAND TO BANK n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle L ...
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NOTE (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ...
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TRUTH TABLE 4 – CURRENT STATE BANK n - COMMAND TO BANK m (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle Row ...
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NOTE (continued): 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the ...
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ABSOLUTE MAXIMUM RATINGS* Voltage Supply DD DD Relative to V ....................................... -1V to +4.6V SS Voltage on Inputs I/O Pins Relative to V ....................................... -1V to +4.6V SS Operating Temperature, T (Commercial) ................................... ...
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CAPACITANCE (Note: 2; notes appear on page 35) PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes 11; notes appear on page 35) AC ...
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AC FUNCTIONAL CHARACTERISTICS (Notes 11; notes appear on page 35) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to ...
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NOTES 1. All voltages referenced This parameter is sampled MHz 25°C; pin under test biased at 1.4V dependent on output loading and cycle DD rates. Specified ...
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INITIALIZE AND LOAD MODE REGISTER CKH t CKS ( ( ) ) CKE ( ( ) ) t CMS t CMH t CMS t CMH ( ( ) ) COMMAND ...
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CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High-Z DQ Two clock cycles Precharge all ...
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CLK CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH DQM/ DQML, DQMH A0-A9, A11, A12 COLUMN ...
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T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM / DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge all ...
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T0 CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE DQM/ DQML, DQMH A0-A9, A11,A12 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK(S) High Precharge all active banks ...
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READ – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ROW A10 DISABLE ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE ROW A10 ...
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SINGLE READ – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ROW A10 ...
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SINGLE READ – WITH AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11 ROW ROW A10 t ...
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ALTERNATING BANK READ ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE ROW ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH COLUMN m 2 A0-A9, A11, A12 ROW ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE ...
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WRITE – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11, A12 ROW ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11, A12 ROW ENABLE AUTO PRECHARGE ROW ...
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SINGLE WRITE – WITHOUT AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ROW A10 ...
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SINGLE WRITE – WITH AUTO PRECHARGE CLK t CKS t CKH CKE t CMS t CMH NOP 4 COMMAND ACTIVE DQM/ DQML, DQMH A0-A9, A11, A12 ROW ...
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ALTERNATING BANK WRITE ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS DQM/ DQML, DQMH A0-A9, A11, A12 ROW ...
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CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ROW A10 ...
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CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP DQM/ DQML, DQMH A0-A9, A11, A12 ROW ROW A10 BA0, BA1 ...
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TYP 0.375 ±0.075 PIN #1 ID NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ...