74ACT16646SSCX Fairchild Semiconductor, 74ACT16646SSCX Datasheet
74ACT16646SSCX
Specifications of 74ACT16646SSCX
Related parts for 74ACT16646SSCX
74ACT16646SSCX Summary of contents
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... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation Features Independent registers for A and B buses ...
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Function Table Inputs G DIR CPAB CPBA SAB ...
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Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( 0. 0. Output Diode Current ( 0. 0. Output ...
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AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL t Clock to Bus PLH t Propagation Delay PHL t Bus to Bus PLH t Propagation Delay PHL t Select to Bus PLH (w/ HIGH or LOW) t Enable ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A 5 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...