74ALVC162839T Fairchild Semiconductor, 74ALVC162839T Datasheet
74ALVC162839T
Manufacturer Part Number
74ALVC162839T
Description
IC SEL RGSTR/BUFF 20B LV 56TSSOP
Manufacturer
Fairchild Semiconductor
Series
74ALVCr
Datasheet
1.74ALVC162839T.pdf
(6 pages)
Specifications of 74ALVC162839T
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
1
Number Of Bits Per Element
20
Current - Output High, Low
12mA, 12mA
Voltage - Supply
1.65 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
© 2001 Fairchild Semiconductor Corporation
74ALVC162839T
74ALVC162839
Low Voltage 20-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs/Outputs
and 26 Series Resistors in the Outputs
General Description
The ALVC162839 contains twenty non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 20-bit word wide mode. All
outputs can be placed into 3-STATE through use of the OE
pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74ALVC162839 is designed for low voltage (1.65V to
3.6V) V
The 74ALVC162839 is also designed with 26
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The 74ALVC162839 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Order Number
CC
applications with I/O compatibility up to 3.6V.
Package Number
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
DS500712
series
Features
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
value of the resistor is determined by the current-sourcing capability of the
driver.
Pin Descriptions
Compatible with PC100 and PC133 DIMM module
specifications
1.65V–3.6V V
3.6V tolerant inputs and outputs
26 series resistors in the outputs
t
Power-off high impedance inputs and outputs
Supports live insertion and withdrawal (Note 1)
Uses patented noise/EMI reduction circuitry
Latchup conforms to JEDEC JED78
ESD performance:
PD
Pin Names
4.6 ns max for 3.0V to 3.6V V
6.3 ns max for 2.3V to 2.7V V
9.8 ns max for 1.65V to 1.95V V
Human body model
Machine model
O
REGE
(CLK to O
I
CLK
0
0
OE
–I
–O
Package Description
19
19
n
CC
)
supply operation
Output Enable Input (Active LOW)
200V
CC
2000V
through a pull-up resistor; the minimum
Register Enable Input
November 2001
Revised November 2001
Description
Clock Input
CC
CC
Outputs
Inputs
CC
www.fairchildsemi.com
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74ALVC162839T Summary of contents
Page 1
... CMOS power dissipation. Ordering Code: Order Number Package Number 74ALVC162839T MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © ...
Page 2
Connection Diagram Logic Diagram www.fairchildsemi.com Truth Table Inputs I CLK REGE Logic HIGH L Logic LOW X Don’t Care, ...
Page 3
Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...
Page 4
AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX Propagation Delay PHL PLH Bus-to-Bus (REGE Propagation Delay PHL PLH Clock to Bus (REGE Propagation Delay PHL PLH REGE ...
Page 5
AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics 1MHz; t Symbol 3.3V 0. FIGURE 2. Waveform ...
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...