74LVT125D,118 NXP Semiconductors, 74LVT125D,118 Datasheet - Page 8

IC BUFF TRI-ST QD N-INV 14SOICN

74LVT125D,118

Manufacturer Part Number
74LVT125D,118
Description
IC BUFF TRI-ST QD N-INV 14SOICN
Manufacturer
NXP Semiconductors
Series
74LVTr
Datasheet

Specifications of 74LVT125D,118

Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 64mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Logic Family
LVT
Number Of Channels Per Chip
4
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Input Bias Current (max)
7000 uA
Low Level Output Current
64 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
2.9 ns (Typ) @ 3.3 V
Number Of Lines (input / Output)
4 / 4
Logical Function
Buffer/Line Driver
Number Of Elements
4
Number Of Channels
4
Number Of Inputs
4
Number Of Outputs
4
Operating Supply Voltage (typ)
3.3V
Package Type
SO
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Quiescent Current
7mA
Technology
BiCMOS
Pin Count
14
Mounting
Surface Mount
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2310-2
74LVT125D-T
935170510118

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVT125D,118
Manufacturer:
NEXPERIA/安世
Quantity:
20 000
Philips Semiconductors
12. Waveforms
74LVT_LVTH125_6
Product data sheet
Fig 6. Propagation delay input (nA) to output (nY)
Fig 7. Enable and disable times of 3-state outputs
V
V
V
V
M
OL
M
OL
= 1.5 V.
= 1.5 V.
and V
and V
nOE input
nY output
nY output
OH
OH
are typical voltage output drop that occur with the output load.
are typical voltage output drop that occur with the output load.
nA input
nY output
Rev. 06 — 6 March 2006
GND
V
V
V
0 V
CC
OH
OL
V
I
GND
V
V
OH
OL
V
I
V
t
M
PLH
t
t
PZH
PZL
V
74LVT125; 74LVTH125
M
V
V
V
M
M
M
V
M
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
t
t
PLZ
V
PHZ
M
t
PHL
mnb072
3.3 V quad buffer; 3-state
V
OL
V
OH
001aac475
0.3 V
0.3 V
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