74ALVC125PW,118 NXP Semiconductors, 74ALVC125PW,118 Datasheet - Page 6

• Manufacturer Part Number: 74ALVC125PW,118
• Description: IC BUFF DVR TRI-ST QD 14TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCr

Specifications of 74ALVC125PW,118

• Package / Case: 14-TSSOP
• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 4
• Number Of Bits Per Element: 1
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Logic Family: ALVC
• Number Of Channels Per Chip: 4
• Polarity: Non-Inverting
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.65 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 24 mA
• Input Bias Current (max): 10 uA
• Low Level Output Current: 24 mA
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Output Current: 50 mA
• Output Type: 3-State
• Output Voltage: 4.6 V
• Propagation Delay Time: 2 ns (Typ) @ 2.7 V or 1.8 ns (Typ) @ 3 V to 3.6 V
• Number Of Lines (input / Output): 4 / 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74ALVC125PW-T; 74ALVC125PW-T; 935269719118

NXP Semiconductors
Table 7.
Voltages are referenced to GND (ground = 0 V). For test circuit see
[1]
[2]
[3]
11. Waveforms
Table 8.
74ALVC125_2
Product data sheet
Symbol
C
Supply voltage
V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
Fig 6. Input nA to output nY propagation delay times
CC
PD
Typical values are measured at T
t
t
t
C
P
f
C
V
N = number of inputs switching
pd
en
dis
i
(C
D
CC
PD
= input frequency in MHz; f
L
is the same as t
is the same as t
= output load capacitance in pF
is the same as t
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts
Measurement points are given in
V
PD
V
OL
Parameter
power dissipation
capacitance
Dynamic characteristics
Measurement points
CC
and V
2
V
CC
f
o
2
OH
) = sum of the outputs
PHL
PZH
f
are the typical output voltage levels that occur with the output load.
PHZ
i
N + (C
and t
and t
and t
Input
V
0.5V
0.5V
1.5 V
1.5 V
M
PLH
PZL
PLZ
o
CC
CC
= output frequency in MHz
L
.
.
.
amb
V
CC
nY output
= 25 C
nA input
2
…continued
Conditions
per buffer; V
Table
outputs HIGH or LOW state
outputs 3-state
f
o
) where:
8.
GND
V
V
OH
OL
V
I
Rev. 02 — 10 January 2008
Output
V
0.5V
0.5V
1.5 V
1.5 V
I
M
= GND to V
CC
CC
D
V
in W).
M
V
M
t
CC
PHL
; V
Figure
CC
= 3.3 V
8.
V
V
V
V
V
X
OL
OL
OL
OL
+ 0.15 V
+ 0.15 V
+ 0.3 V
+ 0.3 V
mna230
t
PLH
[3]
Quad buffer/line driver; 3-state
Min
-
-
40 C to +85 C
74ALVC125
Typ
27
V
V
V
V
V
5
Y
OH
OH
OH
OH
[1]
© NXP B.V. 2008. All rights reserved.
0.15 V
0.15 V
0.3 V
0.3 V
Max
-
-
Unit
pF
pF
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