IS62LV256L-15J Integrated Silicon Solution, IS62LV256L-15J Datasheet
IS62LV256L-15J
Manufacturer Part Number
IS62LV256L-15J
Description
Manufacturer
Integrated Silicon Solution
FEATURES
• High-speed access time: 15, 20, 25 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
• Three-state outputs
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which
may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
SR033-1A
04/27/99
IS62LV256L
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
— 255 mW (max.) operating
— 0.18 mW (max.) CMOS standby
required
FUNCTIONAL BLOCK DIAGRAM
I/O0-I/O7
A0-A14
GND
VCC
CE
OE
WE
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
DESCRIPTION
The
32,768-word by 8-bit static RAM. It is fabricated using
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 15 ns maximum.
When
mode at which the power dissipation is reduced to
50 W (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (
both writing and reading of the memory.
The IS62LV256L is available in the JEDEC standard 28-pin
SOJ and the 450-mil TSOP package.
ISSI
CE
is HIGH (deselected), the device assumes a standby
IS62LV256L is a very high-speed, low power,
MEMORY ARRAY
CE
COLUMN I/O
256 X 1024
). The active LOW Write Enable (
APRIL 1999
ISSI
WE
) controls
ISSI
®
's
1
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