M50FLW040AK1 STMicroelectronics, M50FLW040AK1 Datasheet - Page 12

• Manufacturer Part Number: M50FLW040AK1
• Description: 4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors) 3V Supply Firmware Hub / Low Pin Count Flash Memory
• Manufacturer: STMicroelectronics

M50FLW040A, M50FLW040B
Table 5. Memory Identification Input Configuration (LPC mode)
BUS OPERATIONS
The two interfaces, A/A Mux and FWH/LPC, sup-
port similar operations, but with different bus sig-
nals and timings. The Firmware Hub/Low Pin
Count (FWH/LPC) Interface offers full functional-
ity, while the Address/Address Multiplexed (A/A
Mux) Interface is orientated for erase and program
operations.
See the sections below, The
Pin Count (FWH/LPC) Bus Operations
dress/Address Multiplexed (A/A Mux) Bus Opera-
tions, for details of the bus operations on each
interface.
Firmware Hub/Low Pin Count (FWH/LPC) Bus
Operations
The M50FLW040 automatically identifies the type
of FWH/LPC protocol from the first received nibble
(START nibble) and decodes the data that it re-
ceives afterwards, according to the chosen FWH
or LPC mode. The Firmware Hub/Low Pin Count
(FWH/LPC) Interface consists of four data signals
(FWH0/LAD0-FWH3/LAD3),
(FWH4/LFRAME) and a clock (CLK).
Protection against accidental or malicious data
corruption is achieved using two additional signals
(TBL and WP). And two reset signals (RP and
INIT) are available to put the memory into a known
state.
The data, control and clock signals are designed
to be compatible with PCI electrical specifications.
The interface operates with clock speeds of up to
33MHz.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Standby, Reset and Block Protection.
Bus Read. Bus Read operations are used to read
from the memory cells, specific registers in the
12/52
Memory Number
1 (Boot memory)
2
3
4
5
6
7
8
V
V
V
V
IL
IL
IL
IL
ID2
V
V
V
V
or float
or float
or float
or float
Firmware Hub/Low
one
IH
IH
IH
IH
control
V
V
V
V
IL
IL
IL
IL
and
ID1
or float
or float
V
V
or float
or float
V
V
IH
IH
IH
IH
line
Ad-
V
V
V
V
IL
IL
IL
IL
Command Interface or Firmware Hub/Low Pin
Count Registers. A valid Bus Read operation
starts on the rising edge of the Clock signal when
the
LFRAME, is Low, V
is present on FWH0/LAD0-FWH3/LAD3. On sub-
sequent clock cycles the Host will send to the
memory:
The device responds by outputting Sync data until
the wait states have elapsed, followed by Data0-
Data3 and Data4-Data7.
See
ure
each clock cycle of the transfer. See
and
nals.
Bus Write. Bus Write operations are used to write
to the Command Interface or Firmware Hub/Low
Pin Count Registers. A valid Bus Write operation
starts on the rising edge of the Clock signal when
Input Communication Frame, FWH4/LFRAME, is
Low, V
FWH0/LAD0-FWH3/LAD3. On subsequent Clock
cycles the Host will send to the memory:
The device responds by outputting Sync data until
the wait states have elapsed.
ID0
or float
V
or float
V
or float
V
or float
V
IH
IH
IH
IH
9., for a description of the Field definitions for
ID Select, Address and other control bits on
FWH0-FWH3 in FWH mode.
Type+Dir Address and other control bits on
LAD0-LAD3 in LPC mode.
ID Select, Address, other control bits, Data0-
Data3 and Data4-Data7 on FWH0-FWH3 in
FWH mode.
Cycle Type + Dir, Address, other control bits,
Data0-Data3 and Data4-Data7 on LAD0-
LAD3.
Figure
Table 6.
Input
IL
, and the correct Start cycle is present on
15., for details on the timings of the sig-
and
Communication
A21
1
1
1
1
0
0
0
0
Table
IL
, and the correct Start cycle
8., and
A20
1
1
0
0
1
1
0
0
Figure 7.
Frame,
Table
A19
and
1
0
1
0
1
0
1
0
FWH4/
Fig-
26.,