IDT74LVCH162244APFG IDT, Integrated Device Technology Inc, IDT74LVCH162244APFG Datasheet - Page 5
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
IDT74LVCH162244APFG
Manufacturer Part Number
IDT74LVCH162244APFG
Description
IC BUFF DVR TRI-ST 16BIT 48TVSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74LVCHr
Datasheet
1.IDT74LVCH162244APAG8.pdf
(6 pages)
Specifications of IDT74LVCH162244APFG
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
4
Current - Output High, Low
12mA, 12mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TVSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVCH162244APFG
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; t
SWITCH POSITION
NOTES:
1.
2.
DEFINITIONS:
C
R
IDT74LVCH162244A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
L
T
Symbol
Generator
V
= Termination resistance: should be equal to Z
= Load capacitance: includes jig and probe capacitance.
V
V
For t
For t
LOAD
V
V
C
Pulse
HZ
LZ
IH
T
L
OUTPUT 2
OUTPUT 1
SK
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
(o) OUTPUT1 and OUTPUT2 are any two outputs.
All Other Tests
Disable High
INPUT
(1, 2)
Disable Low
Enable High
Enable Low
Open Drain
V
CC
Test
(1)
= 3.3V±0.3V V
V
300
300
2.7
1.5
50
6
IN
Test Circuit for All Outputs
t
SK
(x)
Output Skew - t
R
= t
T
t
D.U.T.
PLH1
V
PLH2
CC
CC
t
PLH2
(1)
300
300
2.7
1.5
50
6
= 2.7V
-
t
SK
t
PLH1
V
(x)
OUT
OUT
SK
F
F
or
(
≤ 2ns; t
≤ 2.5ns; t
t
X
V
PHL1
of the Pulse Generator.
)
CC
t
C
PHL2
t
PHL2
(2)
L
2 x Vcc
Switch
Vcc / 2
= 2.5V±0.2V
R
V
GND
Open
t
Vcc
150
150
LOAD
SK
-
30
R
≤ 2ns.
t
PHL1
500Ω
≤ 2.5ns.
500Ω
(x)
LVC Link
LVC Link
0V
V
V
V
V
V
V
V
V
T
T
T
IH
OL
OL
OH
OH
GND
V
Open
Unit
mV
mV
pF
V
V
V
LOAD
5
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
ASYNCHRONOUS
SYNCHRONOUS
INPUT TRANSITION
INPUT TRANSITION
OPPOSITE PHASE
NORMALLY
NORMALLY
HIGH-LOW-HIGH
CONTROL
CONTROL
LOW-HIGH-LOW
CONTROL
SAME PHASE
OUTPUT
OUTPUT
TIMING
INPUT
INPUT
DATA
INPUT
HIGH
OUTPUT
LOW
Set-up, Hold, and Release Times
PULSE
PULSE
Enable and Disable Times
CLOSED
SWITCH
SWITCH
Propagation Delay
ENABLE
OPEN
Pulse Width
t
t
PZH
PZL
t
INDUSTRIAL TEMPERATURE RANGE
t
PLH
PLH
t
SU
t
SU
V
0V
V
V
T
T
LOAD/2
t
W
t
REM
t
H
t
PHZ
t
t
DISABLE
PHL
PHL
t
H
t
PLZ
LVC Link
LVC Link
V
LVC Link
V
T
T
LVC Link
V
V
0V
V
V
V
V
V
0V
0V
V
V
V
V
V
V
0V
OH
V
IH
T
T
OL
IH
T
T
IH
OH
LOAD/2
LZ
OL
HZ
0V
0V
0V
0V
V
V
V
V
V
V
V
V
T
T
T
T
IH
IH
IH
IH