STP2003PQFP Sun Microelectronics, STP2003PQFP Datasheet - Page 28
STP2003PQFP
Manufacturer Part Number
STP2003PQFP
Description
PCI I/O Controller
Manufacturer
Sun Microelectronics
Datasheet
1.STP2003PQFP.pdf
(32 pages)
EBus2 Timing
The EBus2 is an asynchronous bus. Its timing is self regulated handshaking, having no fixed relationship to
the PCIO clock.
The EBus2 timing is programmable via three timing control registers in the Ebus2 channel engine. The timing
control registers programming is detailed in the PCIO User’s Manual: see Chapter 7 ”EBus2 Channel
Engine,” section 7.5.2, section 7.6 and section 7.7.
The three timing control registers enable the following functions:
• S
• Minimum deassertion time or R
• W
• Selection of DMA priority algorithm
Figure 4 illustrates the timing parameters which can be controlled through timing control registers.
Timing control registers are programmable at boot time. DO NOT alter them after boot time. The timing given
in the timing control register tables is in terms of the number of EBus2 clocks. Note that the EBus2 clock is the
same as the PCI clock which has a duration of 30ns.
28
EB_CSx_/DACKx_
EB_RD_/EB_WR_
EB_RD_ or EB_WR_ strobes.
ETUP
IDTH
STP2003QFP
T
(Tstrb) of EB_RD_ or EB_WR_ strobes.
IME
(Tsu) and H
OLD
PCIO
PCI I/O Controller
T
Figure 4. Programmable Timing Paramaters
Tsu
IME
ECOVERY
(Thld) of EB_CSx_ or DACKx_ with respect to the
Tstrb
T
IME
(Thld) between consecutive EB_RD_ or EB_WR_ strobes.
Trec
August 2001
Thld