FSTD16211MTDX_NL Fairchild Semiconductor, FSTD16211MTDX_NL Datasheet

FSTD16211MTDX_NL

Manufacturer Part Number

FSTD16211MTDX_NL

Description

24-Bit Bus Switch with Level Shifting

Manufacturer

Fairchild Semiconductor

Datasheet

1.FSTD16211MTDX_NL.pdf (7 pages)

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FSTD16211G

(Note 1)(Note 2)

FSTD16211MTD

(Note 2)

FSTD16211

24-Bit Bus Switch with Level Shifting

General Description

The Fairchild Switch FSTD16211 provides 24-bits of high-

speed CMOS TTL-compatible bus switching. The low On

Resistance of the switch allows inputs to be connected to

outputs without adding propagation delay or generating

additional ground bounce noise. A diode to V

integrated into the circuit to allow for level shifting between

5V inputs and 3.3V outputs.

The device is organized as a 12-bit or 24-bit bus switch.

When OE

nected to Port 1B. When OE

to Port 2B. When OE

exists between the A and B Ports.

Ordering Code:

Note 1: Ordering code “G” indicates Trays.

Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Diagram

Order Number

is LOW, the switch is ON and Port 1A is con-

Package Number

1/2

BGA54A

MTD56

is HIGH, a high impedance state

is LOW, Port 2A is connected

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500313

has been

Features

Voltage level shifting

Minimal propagation delay through the switch

Low l

Zero bounce in flow-through mode

Control inputs compatible with TTL level

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

switch connection between two ports

Package Description

June 2000

Revised April 2005

www.fairchildsemi.com

Related parts for FSTD16211MTDX_NL

FSTD16211MTDX_NL Summary of contents

Page 1

... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 2) Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Diagram © 2005 Fairchild Semiconductor Corporation Features : 4 switch connection between two ports ...

Page 2

Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Name Description Bus Switch Enables 1 2 1A Connect Pin Assignment for FBGA 1 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Switch Voltage (V ) (Note Input Control Pin Voltage (V )(Note Input Diode Current ( Output (I ) ...

Page 4

AC Electrical Characteristics Symbol Parameter Propagation Delay Bus to Bus (Note 9) PHL PLH Output Enable Time PZH PZL Output Disable Time PHZ PLZ Note 9: This parameter is guaranteed by ...

Page 5

Output Voltage HIGH vs. Supply Voltage FIGURE 3. 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A 6 ...

Page 7

Physical Dimensions Physical Dimensions inches (millimeters) unless otherwise noted (Continued) inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch ...

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