MEA-224 Zarlink Semiconductor, Inc., MEA-224 Datasheet - Page 15

• Manufacturer Part Number: MEA-224
• Description: 4-Port, Layer 2 Fast Ethernet Access Controller
• Manufacturer: Zarlink Semiconductor, Inc.

XpressFlow-2001 Series –
Ethernet Switch Chip-set
4.3 XpressFlow Bus Operation
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4.3.1 Pin Description
©
1997
Vertex’s optimized XpressFlow Bus architec-
ture
Provides up to 1.6G bps switching bandwidth
Full multi bus master structure
Allows Access Controllers to communicate
with XpressFlow Engine and other Access
Controllers via a message passing protocol
-33
-40
-50
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ#
S_GNT#
S_OVLD#
S_CLK
(57(; (7:25.6
Symbol
1.07G bps
1.28G bps
1.60G bps
P R E L I M I N A R Y
I/O-OD
I/O-OD
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Output
CMOS
CMOS
CMOS
I/O-TS
I/O-TS
I/O-TS
I/O-TS
Type
Input
Input
Input
Name & Functions
Data Bus Bit [31:0] – a 32-bit synchronous data bus.
Message Envelope – encompasses the entire period of a message
transfer. Targets use the leading edge of this signal to detect the be-
ginning of a message transfer, and to decode the message header for
the intended target(s).
End of Frame – only used by frame data transfer messages to identify
the end of frame condition. This signal is synchronous with the Rx
Frame Status word appended to the end of the message.
Initiator Ready – a normal true signal. When negated, it indicates the
initiator had asserted wait state(s) in between command words. Target
should use this signal as enable signal for latching the data from the
bus.
Target Abort – when asserted, the target had aborted the reception of
current message on the bus.
High Priority Request – indicates one or more Bus Requester is re-
questing for high priority message transfer.
Bus Request – Bus Request signal from Access Controller to Bus Ac-
cess Arbitrator in XpressFlow Engine
Bus Grant – Bus Grant signal from Bus Arbitrator to Bus Requester
Bus Over-load – when asserted, all data forwarding bus bandwidth has
been allocated. Cannot support additional load for data forwarding traf-
fic.
XpressFlow Bus Clock – up to 50MHz system clock
Note:
4-Port 10/100M Ethernet Access Controller
During the system RESET period, Data Bit [31:27] are used
as Processor Interface Configuration bit [0:3]
Page: 15
D A T A
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Two level bus request priorities
High priority for Data Messages
Low priority for Command Messages
for forwarding an Ethernet frame from
receiving port to transmission port
for passing control information between
devices
S H E E T
Rev. 4.0 –December, 1997
EA-224