A3931 Allegro MicroSystems, Inc., A3931 Datasheet - Page 17

• Manufacturer Part Number: A3931
• Description: Automotive 3-Phase BLDC Controller and MOSFET Driver
• Manufacturer: Allegro MicroSystems, Inc.

A3930
A3931
Circuit Layout
Because this is a switch-mode application, where rapid current
changes are present, care must be taken during layout of the
application PCB. The following points are provided as guidance
for layout (refer to figure 3). Following all guidelines will not
always be possible. However, each point should be carefully
considered as part of any layout procedure.
Ground connection layout recommendations:
1.
2.
3.
4.
5.
Subject to Change Without Notice
Preliminary Data Sheet
Sensitive connections such as RDEAD and VDSTH, which
have very little ground current, should be referenced to the
Quiet ground, which is connected independently closest to
the AGND pin. The components associated with these sensi-
tive pins should never be connected directly to the Supply
common or to the Power ground; they must be referenced
directly to the AGND pin.
Supply decoupling for the supply pins VBB, VREG, and
V5 should be connected to Controller Supply ground, which
is connected independently, close to the AGND pin. The
decoupling capacitors should also be connected as close as
possible to the corresponding supply pin.
The oscillator timing components can be connected to Quiet
ground or Controller Supply ground. They should not be
connected to the Supply common or the Power ground.
The exposed thermal pad on the package should be con-
nected to the AGND pin and may form part of the Controller
Supply ground.
If the layout space is limited, then the Quiet ground and the
Controller Supply ground may be combined, provided that
the ground return of the dead-time resistor, RDEAD, is close
to the AGND pin.
April 6, 2006
and
Automotive 3-Phase BLDC Controller
6. The AGND pin should be connected by an independent low
7. Check the peak voltage excursion of the transients on the
Other layout recommendations:
1. Gate charge drive paths and gate discharge return paths may
2. Provide an independent connection from LSS to the common
3. The inputs to the sense amplifier, CSP and CSN, should be
4. Minimize stray inductance by using short, wide copper runs
5. Consider the use of small (100 nF) ceramic decoupling
impedance trace to the Supply common at a single point.
LSS pin with reference to the AGND pin using a close-
grounded (tip and barrel) probe. If the voltage at LSS
exceeds the absolute maximum specified in this datasheet,
add additional clamping, capacitance or both between the
LSS pin and the AGND pin.
carry large transient current pulses. Therefore, the traces
from GHx, GLx, Sx, and LSS should be as short as possible
to reduce the inductance of the circuit trace.
point of the power bridge. It is not recommended to connect
LSS directly to the AGND pin, as this may inject noise into
sensitive functions such as the dead-timer. The LSS connec-
tion should not be used for the CSP connection.
independent traces and for best results should be matched in
length and route.
at the drain and source terminals of all power FETs. This
includes motor lead connections, the input power bus, and
the common source of the low-side power FETs. This will
minimize voltages induced by fast switching of large load
currents.
capacitors across the source and drain of the power FETs
and MOSFET Driver
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
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