A3950SEU-T Allegro MicroSystems, Inc., A3950SEU-T Datasheet
A3950SEU-T
Related parts for A3950SEU-T
A3950SEU-T Summary of contents
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Features and Benefits ▪ Low R outputs DS(on) ▪ Overcurrent protection ▪ Motor lead short-to-supply protection ▪ Short-to-ground protection ▪ Sleep function ▪ Synchronous rectification ▪ Diagnostic output ▪ Internal undervoltage lockout (UVLO) ▪ Crossover-current protection Packages: Package LP, 16 ...
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... A3950 Selection Guide Part Number A3950SLPTR-T 13 in. reel, 4000 pieces / reel A3950SEUTR-T 7 in. reel, 1500 pieces / reel Absolute Maximum Ratings Characteristic Load Supply Voltage Output Current Sense Voltage VBB to OUTx OUTx to SENSE Logic Input Voltage Operating Ambient Temperature Maximum Junction Temperature ...
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... Exposed pad for thermal dissipation connect to GND pins 0.1 μF CP2 VCP Charge Pump 0.1 μF Load Supply VBB Bias 0.1 μF 100 μF OUTA OUTB SENSE VBB OUTA OUTB SENSE GND Description Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 ...
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... Value copper both sides, connected by 43 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com mA mA μ μA μA μA μA μA μ Ω ...
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... A Charge pump and VREG power-on delay (≈200 μs) DMOS Full-Bridge Motor Driver Timing Diagram: PWM Control OutB OutA OutB 8 9 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 ...
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... OUTx ENABLE, Source or Sink BLANK Charge Pump Counter NFAULT Motor lead short condition DMOS Full-Bridge Motor Driver Timing Diagram: Overcurrent Control t t BLANK OCP Normal dc motor capacitance 6 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com ...
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... This output J Function Forward Reverse Brake (slow decay) Fast Decay Synchronous Rectification Fast Decay Synchronous Rectification Sleep Mode Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com ...
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... NFAULT pin is released and normal operation resumes. SHORT T = 1.2 ms OCP Fault asserted , the device will then be allowed OCP 2 μs / div div. Fault asserted 200 μs / div div. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com OCP 8 ...
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... Power dissipation the two sink DMOS drivers DS(on)Source DS(on)Sink 2 R loses × DS(on)Sink Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com (1) (2) 9 ...
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... CP1 and CP2, should be as close to the pins of the device as possible, in order to minimize lead inductance. VBB CVBB1 GND OUTB CVBB1 GND PHASE A3950 GND CP2 EU Package C3 SLEEP CP1 PAD ENABLE OUTB CVBB2 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 10 ...
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... PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals 0.35 0. 3.80 2.15 2.15 3.80 C PCB Layout Reference View Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 11 ...
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... The in for ma tion in clud ed herein is believed rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. ...