CS61305A-IL1 Cirrus Logic, Inc., CS61305A-IL1 Datasheet
CS61305A-IL1
Related parts for CS61305A-IL1
CS61305A-IL1 Summary of contents
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... Applications Interfacing network transmission equipment such as SONET multiplexor and M13 to a DSX-1 cross con- nect. Interfacing customer premises equipment to a CSU. ORDERING INFORMATION CS61305A-IP1 CS61305A-IL1 (CLKE) (INT) XTALIN XTALOUT MODE TAOS LEN0 9 10 ...
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... TV+, RV+ = 5.0V 5%; GND = 0V) Symbol Min (Notes 2.0 IH (Notes (Notes 2.4 OH (Notes (RV+) - 0.2 IH (Note OUT CS61305A Min Max Units - 6 (RV+) + 0.3 V (RV+) + 0 -65 150 C Typ Max Units 5.0 5. ...
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... ABS((z +z )/( where series resistors terminated resistor across the secondary of the transmitter transformer CS61305A Min Typ Max 2.14 2.37 2.6 2.7 3.0 3.3 2.7 3.0 3.3 2.4 3.0 3.6 -0.237 - 0.237 -0 ...
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... CS61305A Typ Max Units 50k - - - peak peak 175 190 bits - ...
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... The maximum gap size that can pw2 CS61305A Min Typ Max Units - 6.176000 - MHz 1.544 - MHz 320 648 980 ns 130 190 ...
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... RPOS RNEG RDATA BPV RCLK Figure 2. Recovered Clock and Data Switching Characteristics 6 ( TV+, RV+ = 5%; Symbol (Note 31 90% 10% Figure 1. Signal Rise and Fall Characteristics t pw1 t pwl1 t pwh1 t t su1 h1 CS61305A Min Typ Max cdh t 240 - cl t 240 - ch t ...
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... Figure 3b. Alternate External Clock Characteristics cdh LSB BYTE DATA Figure 4. Serial Port Write Timing Diagram t cdv Figure 5. Serial Port Read Timing Diagram PCS t su4 t pcsl VALID INPUT DATA CS61305A t pw3 t pwh3 ACLKI t cwh t cch t cdh MSB BYTE t cdz HIGH ...
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... THEORY OF OPERATION Key Enhancements of the CS61305A Relative to the LXT305A 12.5% lower power consumption transmitter short-circuit current RMS limiting for E1 (per OFTEL OTR-001), Optional AMI, B8ZS, HDB3 encoder/de- coder or external line coding support, Receiver AIS (unframed all ones) detection, Improved receiver Loss of Signal handling ...
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... ATTENUATOR CS61305A AIS LINE RECEIVER DETECT AIS HOST MODE CLKE CONTROL JITTER LINE DRIVER ATTENUATOR DRIVER MONITOR CS61305A LINE RECEIVER Figure 7. Overview of Operating Modes CS61305A LEN0/1/2 TTIP TRANSMIT TRING TRANSFORMER MRING MTIP DPM RTIP RECEIVE RRING TRANSFORMER LEN0/1/2 TTIP TRANSMIT TRING ...
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... OFTEL OTR-001 short-circuit current limiting require- ments for E1 applications. The CS61305A will detect a static TCLK, and will force TTIP and TRING low to prevent trans- mission when data is not present. When any transmit control pin (TAOS, LEN0-2 or LLOOP) is toggled, the transmitter outputs will require ap- proximately 22 bit periods to stabilize ...
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... TRING). In this mode, the TPOS and TNEG (or TDATA) inputs are ignored. A TAOS request will be ignored if remote loopback is in effect. ACLKI jitter will be attenuated. TAOS is not available on the CS61305A when ACLKI is grounded. Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) ...
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... Crystal Semiconductor offers the CXT6176 & CXT8192 crystals, which yield optimum performance with the CS61305A. Receiver The receiver extracts data and clock from an AMI (Alternate Mark Inversion) coded signal and out- puts clock and synchronized data ...
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... In the Host Mode, CLKE determines the clock polarity for which output data is stable and valid as shown in Table 5. Jitter and Recovered Clock The CS61305A is designed for error free clock and data recovery from an AMI encoded data MODE (pin 5) LOW (< ...
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... Theoretically, this would give a jitter tolerance of 0.46 UI. The actual jitter tolerance of the CS61305A is only slightly less than the ideal. In the event of a maximum jitter hit, the RCLK clock period immediately adjusts to align itself ...
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... DPM is available from both the register and pin TCLK 11. Whenever more than one line interface IC resides on the same circuit board, the effectiveness of the driver performance monitor can be maximized by having each IC monitor performance of a neigh- boring IC, rather than having it monitor its own performance. CS61305A 15 ...
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... LOS high. Serial Interface In the Host Mode, pins 23 through 28 serve as a microprocessor/microcontroller interface. One on-board register can be written to via the SDI pin or read from via the SDO pin at the clock rate determined by SCLK. Through this register, a CS61305A DS157PP3 ...
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... Bits D0 and D1 are used to clear an interrupt is- sued from the INT pin, which occurs in response to a loss of signal or a problem with the output driver. Writing a "1" to either "Clear LOS" or "Clear DPM" over the serial interface has three effects: CS61305A ...
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... Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering CS61305A Status occured. occured. last "clear LOS" and "clear DPM". Table 12. Output Data Register (bits D5-D7) DS157PP3 ...
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... TPOS PLCC 7 top 8 view DPM LOS TTIP CS61305A Extended Hardware TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP MRING PCS MTIP RCODE TRING TV+ Hardware Extended Hardware TAOS LLOOP RLOOP LEN2 26 25 LEN1 ...
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... INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor (47k - 100k). 20 CS61305A DS157PP3 ...
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... Clock used to read or write the serial port registers. SCLK can be either high or low when the line interface is selected using the CS pin. SDI - Serial Data Input, Pin 24. (Host Mode) Input for the input data register. Sampled on the rising edge of SCLK. DS157PP3 CS61305A 21 ...
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... TPOS/TNEG or TDATA are sampled on the falling edge of TCLK. TDATA - Transmit Data, Pin 3. (Extended Hardware Mode) Data to be transmitted by the TTIP and TRING outputs is input in NRZ format at this pin, after being encoded by the line code encoder. TDATA is sampled on the falling edge of TCLK. 22 CS61305A DS157PP3 ...
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... These pins are normally connected to TTIP and TRING and monitor the transmitter output. If the INT pin in the Host mode is used, and the monitor is not used, writing a "1" to the "clear DPM" bit will prevent an interrupt from the driver performance monitor. DS157PP3 CS61305A 23 ...
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... DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. B D2/ pin E1 Plastic DIP 28-pin PLCC E E1 DIM MIN A 4.20 A1 2.29 B 0.33 D/E 12.32 D1/E1 11.43 D1 D2/E2 9. CS61305A MILLIMETERS DIM MIN NOM MAX MIN 3.94 4.32 5.08 0.155 A A1 0.51 0.76 1.02 0.020 B 0.36 0.46 0.56 0.014 B1 1.02 1.27 1.65 0.040 C 0.20 0.25 0.38 0.008 36.45 36.83 D 37.21 1.435 E1 13.72 13.97 14 ...
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... Table A1. External Component Values Mode. Figure A4 illustrates the Extended Hardware Mode. The receiver transformer has a grounded center tap on the IC side. Resistors between the RTIP and RRING pins to ground provide the termina- tion for the receive line. CS61305A 2 RECEIVE LINE 6 2CT:1 2 ...
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... Transformers Recommended transmitter and receiver trans- former specifications are shown in Table A2. The transformers in Table A3 are recommended for use with the CS61305A. Refer to the "Telecom Transformer Selection Guide" for detailed sche- matics which show how to connect the line interface IC with a particular transformer. ...
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... IN AIS EXTENDED 5 MODE HARDWARE 4 RRING TCODE MODE 7 RDATA 8 RCLK 3 TDATA TRING 2 TCLK TTIP 9 XTALIN 10 XTALOUT RGND TGND Extended Hardware Mode Configuration CS61305A 23 Line 24 Length 25 Setting 240 3 RECEIVE 6 LINE 240 20 5 2CT:1 PE-65351 TRANSMIT LINE 1:1 ...
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... If the line interface is used in Hardware mode, then the line interface RCLK output must be inverted be- fore being input to the CS62180B. If the CS61305A is used in Extended Hardware Mode, the RCLK output does not have to be inverted before being input to the CS62180B. 28 ...
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... Bel Fuse S553-0013-06 Pulse Engineering PE-65766 Bel Fuse S553-0013-07 Pulse Engineering PE-65835 Pulse Engineering PE-65839 Table A3. Recommended Transformers CS61305A Package Type 1.5 kV through-hole, single 1.5 kV through-hole, single 1.5 kV through-hole, single 1.5 kV through-hole, dual 1.5 kV through-hole, dual 1.5 kVsurface-mount, dual 1.5 kV surface-mount, dual 3 kV through-hole, single EN60950, EN41003 approved ...
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Notes • ...
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... ORDERING INFORMATION: CDB61534, CDB6158, CDB61574A, CDB61575, CDB61304A, CDB61305A +5V 0V Reset Circuit CS61534, CS61535, CS61535A, CS6158, CS6158A, CS61574, CS61574A, CS61575, CS61577, CS61304A or CS61305A coax E1, or 120 twisted-pair E1 operation. CDB61535. CDB61535A, CDB6158A, CDB61574, CDB61577, TTIP TRING RTIP RRING XTL twisted-pair SEP ’95 DS40DB3 31 ...
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... SW1 and jump- ers JP2, JP6, and JP7. The CS61535A, CS61574A, CS61575, CS61577, CS61304A, and CS61305A support the Hardware, Extended Hardware, and Host operating modes. The CS61534, CS61535, and CS61574 support the Hardware and Host operating modes. The CS6158 and CS6158A only support the Hardware operating mode ...
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... LOS applications with the CS61534, 12 CS61535, CS6158, CS61574, RV+ RV+ OR CS61577) LOS Q2 Q1 2N2222 2N2222 U1: CS61534, CS61535, LED LED CS61535A, CS6158 CS6158A, CS61574, CS61574A, CS61575 470 470 CS61577, CS61304A, OR CS61305A RV+ T2 RTIP 2:1 RRING TTIP JP5 (see Table 2) TRING 33 ...
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Performance Monitor alarm. The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Extended Hardware Mode In the Extended Hardware operating mode, the line interface is configured using DIP switch S2. The digital control ...
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The evaluation board supports 100 T1, 75 coax E1, and 120 eration. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The ...
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A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match ...
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TRANSFORMER 1,2 (Turns Ratio) PE-65351 (1:2CT) Schott 12930 (1:2CT) PE-65388 (1:1.15) Schott 12931 (1:1.15) PE-65389 (1:1:1.26) Schott 12932 (1:1:1.26) PE-64951 (dual 1:2CT) Schott 11509 (dual 1:2CT) PE-65565 (dual 1:1.15 & 1:2CT) Schott 12531 (dual 1:1.15 & 1:2CT) PE-65566 (dual 1:1:1.26 ...
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LINE INTERFACE EVALUATION BOARD Figure 2. Silk Screen Layer (NOT TO SCALE) DS40DB3 ...
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Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS40DB3 LINE INTERFACE EVALUATION BOARD 39 ...
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LINE INTERFACE EVALUATION BOARD Figure 4. Bottom Trace Layer (NOT TO SCALE) DS40DB3 ...
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Notes • ...
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Notes • ...
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Notes • ...
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TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...