CS61310-IP Cirrus Logic, Inc., CS61310-IP Datasheet - Page 6
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CS61310-IP
Manufacturer Part Number
CS61310-IP
Description
T1 line interface unit
Manufacturer
Cirrus Logic, Inc.
Datasheet
1.CS61310-IP.pdf
(30 pages)
T1 SWITCHING CHARACTERISTICS
GND = 0 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+; See Figures 1, 2, & 3)
Notes: 17. MCLK provided by an external source or TCLK.
6
TCLK Frequency
TCLK Duty Cycle
MCLK Frequency
RCLK Duty Cycle
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG Hold Time
RPOS/RNEG Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
18. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator FIFO limits are reached.
19. At max load of 1.6 mA and 50 pF.
20. Host Mode (CLKE = 1).
21. Host Mode (CLKE = 0). )
RCLK
RPOS
RNEG
RCLK
Parameter
Figure 2. Recovered Clock and Data Switching Characteristics
Figure 3. Transmit Clock and Data Switching Characteristics
Any Digital Output
Figure 1. Signal Rise and Fall Characteristics
TPOS/TNEG
t pwl1
t
su1
TCLK
(Notes 12, 18) t
t pw1
t r
(Note 12) t
(Note 17)
(Note 19)
(Note 19)
(Note 20)
(Note 21)
(Note 20)
(Note 21)
10%
t
t pwh1
h1
(TA = -40 C to 85 C; TV+, RV+ = 5.0 V 5%;
t pwh2
t su2
90%
t pw2
Symbol
pwh2
pwh1
t h2
f
t
t
t
f
mclk
t
t
t
su2
su1
su1
tclk
h2
h1
h1
t
t
r
f
/t
/t
90%
pw2
pw1
10%
t f
Min
150
150
150
150
45
45
25
25
-
-
-
-
(CLKE = 1)
(CLKE = 0)
1.544
1.544
Typ
274
274
274
274
50
50
-
-
-
-
CS61310
Max
55
55
85
85
-
-
-
-
-
-
-
-
DS440PP2
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
%
%