CS61584A-IL5 Cirrus Logic, Inc., CS61584A-IL5 Datasheet - Page 26

• Manufacturer Part Number: CS61584A-IL5
• Description: Interface, Dual T1/E1 Line Interface
• Manufacturer: Cirrus Logic, Inc.

AAO: The Automatic All-Ones (AAO) bit in the
Mask Register (Channel 1, bit 1) causes an un-
framed all-ones pattern to be output at the RPOS
and RNEG (or RDATA) pins when the receiver is
in a loss of signal (LOS) condition.
9.1.3
The Control A registers are read-write registers and
are shown in Table 7. The Control A registers se-
lect device configuration and power down control.
CLKE: Establishes the edge of the of RCLK that
RPOS and RNEG (or RDATA) are valid.
PD: Controls per channel power down.
ATTEN0 and ATTEN1: Controls the jitter attenu-
ator location and -3 dB knee frequency (See Jitter
Attenuator section).
26
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Control A Registers
CLKE
PD1
ATTEN01
ATTEN11
CODER1
AMI-T1
AMI-R1
Factory Test
EXZ
PD2
ATTEN02
ATTEN12
CODER2
AMI-T2
AMI-R2
Factory Test
Description
Description
Serial Port Address: 0x14; Parallel Port Address: 0xY4
Serial Port Address: 0x15; Parallel Port Address: 0xY5
RPOS/RNEG (or RDATA) valid on
falling edge of RCLK
Power down channel
Coder mode enabled
AMI encoder enabled
AMI decoder enabled
Test
Excessive zeros detection for both
channels enabled
Power down channel
Coder mode enabled
AMI encoder enabled
AMI decoder enabled
Test
Control A Register (Channel 1)
Control A Register (Channel 2)
Table 7. Control A Registers
1
1
DS261PP5
(See Jitter Attenuator section)
(See Jitter Attenuator section)
Jitter attenuator location
Jitter attenuator location
CODER: Controls the coder mode function. The
TPOS, TNEG, RPOS, and RNEG pins are active
when the transparent mode is enabled. The TDA-
TA, RDATA, AIS, and BPV pins are active when
the coder mode is enabled.
AMI-T: Controls the line encoder in the transmit
direction. The selection of B8ZS or HDB3 is deter-
mined by the CON[3:0] bits (See the Transmitter
section).
AMI-R: Controls the line decoder in the receive di-
rection. The selection of B8ZS or HDB3 is deter-
mined by the CON[3:0] bits (See the Transmitter
section).
EXZ: Controls the automatic detection of excessive
zeros on the BPV pin according to ANSI T1.231
when coder mode is enabled (CODERx = 1).
Definition
Definition
RPOS/RNEG (or RDATA) valid on
rising edge of RCLK
Power up channel
Transparent mode enabled
B8ZS/HDB3 encoder enabled
B8ZS/HDB3 decoder enabled
Normal operation
Excessive zeros detection for both
channels disabled
Power up channel
Transparent mode enabled
B8ZS/HDB3 encoder enabled
B8ZS/HDB3 decoder enabled
Normal operation
0
0
CS61584A
DS261PP5
Reset
Reset
Value
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0