STG3000X STMicroelectronics, STG3000X Datasheet - Page 68
STG3000X
Manufacturer Part Number
STG3000X
Description
128-BIT 3D MULTIMEDIA ACCELERATOR
Manufacturer
STMicroelectronics
Datasheet
1.STG3000X.pdf
(77 pages)
- Current page: 68 of 77
- Download datasheet (2Mb)
RIVA 128
Byte offsets 0x13 - 0x10
Base Memory Address Register (0x13 - 0x10)
68/77
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:24
23:4
Bits
2:1
3
0
0x13
Function
The BASE_ADDRESS bits contain the most significant bits of the base
address of the device. This indicates that the RIVA 128 requires a 16MByte
block of contiguous memory beginning on a 16MByte boundary. This memory
range contains memory-mapped registers and FIFOs and should not be set
as part of a PentiumPro™’s write combining range.
The BASE_RESERVED bits form the least significant bits of the base address
and are hardwired to 0.
The PREFETCHABLE bit indicates that there are no side effects on reads,
that the device returns all bytes on reads regardless of the byte enables, and
that host bridges can merge processor writes into this range without causing
errors.
The ADDRESS_TYPE bits contain the type (width) of the Base Address.
0=32-bit
The SPACE_TYPE bit indicates whether the register maps into Memory or I/O
space.
0=Memory space
0x12
128-BIT 3D MULTIMEDIA ACCELERATOR
0x11
9
8
7
6
5
0x10
4
3
R W 0
R W I
R - 0
R - 1
R - 0
R - 0
2
1
0
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