PM5361-RI PMC-Sierra, Inc., PM5361-RI Datasheet - Page 39
PM5361-RI
Manufacturer Part Number
PM5361-RI
Description
SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR
Manufacturer
PMC-Sierra, Inc.
Datasheet
1.PM5361-RI.pdf
(108 pages)
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DATA SHEET
PMC-920526
INCIC1J1:
INCISPE:
AUTOAIS:
IPE:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
expected to be odd. When IOP is set low, the expected parity is even.
Membership of the parity signal set always includes DIN[7:0], and may
include input signals IC1J1 and ISPE as controlled by the INCIC1J1 and
INCISPE bits, respectively.
The INCIC1J1 bit controls the whether the 1C1J1 input signal participates in
the incoming parity calculations. When INCIC1J1 is set high, the parity signal
set includes the IC1J1 input. When INCIC1J1 is set low, parity is calculated
without regard to the state of IC1J1. Selection of odd or even parity is
controlled by the IOP bit.
The INCISPE bit controls the whether the ISPE input signal participates in the
incoming parity calculations. When INCISPE is set high, the parity signal set
includes the ISPE input. When INCISPE is set low, parity is calculated
without regard to the state of ISPE. Selection of odd or even parity is
controlled by the IOP bit.
The AUTOAIS bit is an active high AIS insertion enable. When AUTOAIS is
set high, AIS is automatically generated on the outgoing data stream for all
tributaries that exhibit a LOP state. When AUTOAIS is set low, the generation
of AIS on the outgoing data stream is inhibited. The negation of AIS occurs
at tributary multiframe boundaries.
The IPE bit is an active high interrupt enable. When IPE is set high, the
occurrence of a parity error on the incoming parity signal set will cause an
interrupt to be asserted on the interrupt (INTB) output. When IPE is set low,
incoming parity errors will not cause an interrupt.
ISSUE 8
TRIBUTARY UNIT PAYLOAD PROCESSOR
31
PM5361 TUPP
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