MD1210 Supertex, Inc., MD1210 Datasheet - Page 5

• Manufacturer Part Number: MD1210
• Description: High Speed Dual Mosfet Driver
• Manufacturer: Supertex, Inc.

Application Information
For proper operation of the MD1210, low inductance bypass
capacitors should be used on the various supply pins. The
GND input pin should be connected to the digital ground.
The IN
source with a swing of GND to logic level high, which is 1.2V
to 5.0V. Good trace practices should be followed correspond-
ing to the desired operating speed. The internal circuitry of
the MD1210 is capable of operating up to 100MHz, with the
primary speed limitation being the loading effects of the load
capacitance. Because of this speed and the high transient
currents that result with capacitive loads, the bypass capaci-
tors should be as close to the chip pins as possible. The V
V
connections directly to a ground plane. The power connec-
tions V
to the ground plane with short leads and decoupling compo-
nents to prevent resonance in the power leads. A common
capacitor and voltage source may be used for these two
pins, which should always have the same DC voltage ap-
plied. For applications sensitive to jitter and noise, separate
decoupling networks may be used for V
Pin Description
Note:
SS2
Pin #
10
12
1 Thermal Pad and Pin #5 (V
2 Index Pad and Thermal Pad are connected internally
11
1
2
3
4
5
6
7
8
9
, and V
A
DD1
, IN
Name Description
and V
OUT
OUT
GND
V
V
V
V
B
IN
OE
L
IN
V
V
, and OE pins should be connected to their logic
SS1
SS2
DD2
DD1
pins should have low inductance feed-through
H
L
A
B
B
A
DD2
Logic input. Controls OUT
logic low will cause the output to swing to V
Supply voltage for N-channel output stage.
Logic input. Controls OUT
logic low will cause the output to swing to V
Logic input ground reference.
Low side analog circuit and level shifter supply voltage. Should be at the same potential as V
Low side gate drive supply voltage.
Output driver. Swings from V
series capacitor. When OE is low, the output is disabled. OUT
N-channel MOSFET.
Supply voltage for P-channel output stage.
Output driver. Swings from V
series capacitor. When OE is low, the output is disabled. OUT
P-channel MOSFET.
High side gate drive supply voltage.
High side analog circuit and level shifter supply voltage. Should be at the same potential as V
Output-enable logic input. When OE is high, (V
level high and low for IN
and IN
should have a ceramic bypass capacitor
B
SS1
) must be connected externally.
DD1
and V
A
A
B
and IN
when OE is high. Input logic high will cause the output to swing to V
when OE is high. Input logic high will cause the output to swing to V
H
H
DD2
to V
to V
B
.
. When OE is low, OUT
L
L
. Intended to drive the gate of an external N-channel MOSFET via a
. Intended to drive the gate of an external P-channel MOSFET via a
SS1
,
5
H
H
The V
2.0A, so they should be provided with an appropriate bypass
capacitor located next to the chip pins. A ceramic capacitor
of up to 1.0µF may be appropriate, with a series ferrite bead
to prevent resonance in the power supply lead coming to the
capacitor. Pay particular attention to minimizing trace lengths
and using sufficient trace width to reduce inductance. Sur-
face mount components are highly recommended. Since the
output impedance of this driver is very low, in some cases it
may be desirable to add a small series resistor in series with
the output signal to obtain better waveform integrity at the
load terminals. This will of course reduce the output voltage
slew rate at the terminals of a capacitive load.
Pay particular attention to the parasitic coupling from the
driver output to the input signal terminals. This feedback
may cause oscillations or spurious waveform shapes on the
edges of signal transitions. Since the input operates with sig-
nals down to 1.2V even small coupled voltages may cause
problems. Use of a solid ground plane and good power and
signal layout practices will prevent this problem. Be careful
that the circulating ground return current from a capacitive
load cannot react with common inductance to cause noise
voltages in the input logic circuitry.
.
.
OE
H
+ V
and V
GND
)/2 sets the threshold transition between logic
A
L
is at V
pins can draw fast transient currents of up to
A
B
will swing to V
will swing to V
H
and OUT
B
is at V
H
L
turning off the external
turning off the external
L
regardless of IN
MD1210
SS2
DD2
L
.
L
.
. Input
. Input
A