AD9393 Analog Devices, Inc., AD9393 Datasheet
AD9393
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AD9393 Summary of contents
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... HDCP 1.1 protocol. Fabricated in an advanced CMOS process, the AD9393 is provided in a space-saving 76-ball, surface-mount, Pb-free, ball grid array (BGA) and is specified over the −10°C to +80° ...
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... Outputs (Both Data and Clocks) .............................................. 33 Digital Inputs .............................................................................. 33 Color Space Converter (CSC) Common Settings ...................... 34 HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9393) ................................................................................ 34 HDTV YCrCb (16 to 235) to RGB (0 to 255)......................... 34 SDTV YCrCb (0 to 255) to RGB (0 to 255) ............................ 34 SDTV YCrCb (16 to 235) to RGB (0 to 255) .......................... 35 RGB (0 to 255) to HDTV YCrCb (0 to 255) ...
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... THERMAL CHARACTERISTICS θ Junction-to-Ambient JA θ Junction-to-Case JC Temp Test Level Min Full VI 2.6 Full VI Full V Full V 25°C V Full VI V − 0.1 DD Full VI Full Rev Page AD9393 Typ Max Unit V 0.8 V −82 μA 82 μ 0 Binary 59 °C/W 15.2 °C/W ...
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... AD9393 DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS =3 1.8 V, unless otherwise noted Table 2. Parameter DC DIGITAL I/O Specifications High-Level Input Voltage ( Low-Level Input Voltage ( High-Level Output Voltage ( Low-Level Output Voltage ( SPECIFICATIONS Output High Level OHD OUT OH Output Low Level ...
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... Parameter is guaranteed by design and characterization 20 mA testing. −25°C to +85°C −65°C to +150°C V Parameter is a typical value only. 150°C VI 100% production tested at 25°C; guaranteed by design 150°C and characterization testing. ESD CAUTION Rev Page AD9393 ...
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... D15 D16 D18 D20 D22 DCLK D12 D17 D19 D21 D23 DE D10 GND GND GND V D AD9393 TOP VIEW (Not to Scale) D4 GND SCLK LRCLK MCLK I2S3 I2S2 I2S1 I2S0 SPDIF RxC+ GND Rx0– Rx0+ GND Rx1– ...
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... AD9393 is interfacing with lower voltage logic, V lower supply voltage (as low as 1.8 V) for compatibility. PLL Power Supply (1.8 V). The most sensitive portion of the AD9393 is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The user should provide quiet, noise-free power to these pins ...
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... OUTPUT SIGNAL HANDLING The digital outputs operate from 1 3 POWER MANAGEMENT To determine the correct power state, the AD9393 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down ball ...
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... The AD9393 contains a filter that allows it to convert a signal from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the maximum accuracy and fidelity of the original signal. Input Color Space to Output Color Space The AD9393 can accept a wide variety of input formats and either retain that format or convert to another. Input formats supported are • ...
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... AD9393, refer to the AN-795 Application Note, AD9880 Color Space Converter User's Guide. AUDIO PLL SETUP Data contained in the audio infoframes (among other registers) defines for the AD9393 HDMI receiver not only the type of Table 7. Audio Register Settings Recommended Register Bits ...
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... NDF registers to see if there is new information to be processed. OUTPUT DATA FORMATS The AD9393 supports 4:4:4, 4:2:2, double data-rate (DDR), and BT656 output formats. Register 0x25[3:0] controls the output mode. These modes and the pin mapping are illustrated in Table 8. ...
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... AD9393 2-WIRE SERIAL REGISTER MAP The AD9393 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 9. Control Register Map Hex Address Read/Write Bits ...
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... Returns HDMI HSYNC polarity. Returns HDMI VSYNC polarity. Returns current HDMI pixel repetition amount 1× 2× … The clock and data outputs are automatically decimated by this value. AD9393 ...
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... AD9393 Hex Address Read/Write Bits 0x34 Read/write [5:4] [3] [2] [1] 0x35 Read/write [6:5] [4:0] 0x36 Read/write [7:0] 0x37 Read/write [4:0] 0x38 Read/write [7:0] 0x39 Read/write [4:0] 0x3A Read/write [7:0] 0x3B Read/write [4:0] 0x3C Read/write [7:0] 0x3D Read/write [4:0] 0x3E Read/write [7:0] 0x3F Read/write [4:0] 0x40 Read/write [7:0] 0x41 Read/write [4:0] 0x42 Read/write [7:0] 0x43 Read/write [4:0] 0x44 Read/write [7:0] 0x45 ...
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... These seven bits are updated if any specific packet has been received since last reset or loss of clock detect. Normal is 0x00. Bit Data Packet Detected 0 AVI infoframe. 1 Audio infoframe. 2 SPD infoframe. 3 MPEG source infoframe. 4 ACP packets. 5 ISRC1 packets. 6 ISRC2 packets DVI HDMI. AD9393 . S ...
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... AD9393 Hex Address Read/Write Bits 0x5E Read [7:6] [5:3] [2] [1] [0] Audio Channel Status 0x5F Read [7:0] 0x60 Read [7:4] [3:0] 0x61 Read [5:4] [3:0] 0x62 Read [3:0] 0x7B Read [7:0] 0x7C Read [7:0] 0x7D Read [7:4] Read [3:0] 0x7E Read [7:0] 0x7F Read [7:0] AVI Infoframe 0x80 Read [7:0] Default Value Register Name 0 Channel status 0 PCM audio data ...
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... Normal (no NDFs) is 0x00. When any NDF register is read, all bits reset to 0x00. All NDF registers contain the same data. Bit Data Packet Changed 0 AVI infoframe. 1 Audio infoframe. 2 SPD infoframe. 3 MPEG source infoframe. 4 ACP packets. 5 ISRC1 packets. 6 ISRC2 packets. AD9393 ...
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... AD9393 Hex Address Read/Write Bits 0x88 Read [7:0] 0x89 Read [7:0] 0x8A Read [7:0] 0x8B Read [7:0] 0x8C Read [7:0] 0x8D Read [7:0] 0x8E Read [7:0] 0x8F Read [6:0] 0x90 Read [7:0] 0x91 Read [7:4] [2:0] 0x92 Read [4:2] [1:0] 0x93 Read [7:0] 0x94 Read [7:0] 0x95 Read [7] [6:3] Default Value Register Name 0 Active line start MSB ...
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... HDD video. 0x05 = DVC. 0x06 = DSC. 0x07 = video CD. 0x08 = game. 0x09 = PC general. New data flags (see Register 0x87). MB[0] (lower byte of MPEG bit rate in hertz). This is the lower eight bits of 32 bits (4 bytes) that specify the MPEG bit rate in hertz. MB[1]. MB[2]. MB[3] (upper byte). AD9393 ...
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... AD9393 Hex Address Read/Write Bits 0xBD Read [4] [1:0] 0xBE Read [7:0] 0xBF Read [6:0] 0xC0 Read [7:0] 0xC1 Read [7:0] 0xC2 Read [7:0] 0xC3 Read [7:0] 0xC4 Read [7:0] 0xC5 Read [7:0] 0xC6 Read [7:0] 0xC7 Read [6:0] 0xC8 Read [7] [6] [2:0] 0xC9 Read [7:0] 0xCA Read [7:0] 0xCB Read [7:0] 0xCC Read [7:0] 0xCD Read [7:0] 0xCE ...
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... Default Value Register Name 0 ISRC2_PB6 0 ISRC2_PB7 0 ISRC2_PB8 0 ISRC2_PB9 0 New data flags 0 ISRC2_PB10 0 ISRC2_PB11 0 ISRC2_PB12 0 ISRC2_PB13 0 ISRC2_PB14 0 ISRC2_PB15 0 ISRC2_PB16 Rev Page Description ISRC2_PB6. ISRC2_PB7. ISRC2_PB8. ISRC2_PB9. New data flags (see Register 0x87). ISRC2_PB10. ISRC2_PB11. ISRC2_PB12. ISRC2_PB13. ISRC2_PB14. ISRC2_PB15. ISRC2_PB16. AD9393 ...
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... These bits are an 8-bit register that sets the duration of the HSYNC output pulse. The leading edge of the HSYNC output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9393 then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the HSYNC output, which is also phase- adjusted. The power-up default is 32. 0x24— ...
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... This bit sets the LSB of the address of the HDCP only for a second receiver in a dual-link configuration. The power-up default is 0. 0x27—Bit[5], Clock Test The power-up default setting pins are in Rev Page AD9393 2 C. Set this bit ...
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... AD9393 BT656 GENERATION 0x27—Bit[4], BT656 EN This bit enables the output to be BT656-compatible with the defined start of active video (SAV) and the end of active video (EAV) controls to be inserted. These require specification of the number of active lines, active pixels per line, and delays to place these markers ...
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... R = (A1 × (A2 × G OUT (B1 × (B2 × G OUT (C1 × (C2 × G OUT IN The default value for the 13-bit A2 coefficient is 0x0800. Rev Page AD9393 ) + (A3 × (B3 × (C3 × (A3 × (B3 × B ...
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... AD9393 0x39—Bits[4:0], CSC_COEFF_A3 MSB and 0x3A— Bits[7:0], CSC_COEFF_A3 LSB The default value for the 13-bit A3 is 0x00000. 0x3B—Bits[4:0], CSC_COEFF_A4 MSB and 0x3C— Bits[7:0], CSC_COEFF_A4 LSB The default value for the 13-bit A4 is 0x19D7. 0x3D—Bits[4:0], CSC_COEFF_B1 MSB and 0x3E— ...
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... AAC 0x7 DTS 0x8 ATRAC 0x91—Bits[2:0], Audio Channel Count These bits specify how many audio channels (2 channels to 8 channels) are being sent. Table 22. CC[2:0] Channel Count 000 Refer to stream header 001 2 010 3 011 4 100 5 101 6 110 7 111 8 Rev Page AD9393 ...
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... AD9393 0x93—Bits[7:0], Maximum Bit Rate For compressed audio only, when this value is multiplied by 8 kHz, it represents the maximum bit rate. A value of 0x08 in this field yields a maximum bit rate of (8 kHz × 8 kHz = 64 kHz). 0x94—Bits[7:0], Speaker Mapping Bits[4:0] define the suggested placement of speakers. Bits[7:5] are currently not available ...
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... Reserved for super audio CD (SACD) 0x04 to 0xFF Reserved 0xC7—Bits[6:0], New Data Flags See the 0x87—Bits[6:0], New Data Flags (NDF) section for a description. 0xC8—Bit[7], ISRC1 Continued This bit indicates that a continuation of the 16 ISRC1 packet bytes (an ISRC2 packet) is being transmitted. Rev Page AD9393 ...
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... AD9393 0xC8—Bit[6], ISRC1 Valid This bit is an indication of whether the ISRC1 packet bytes are valid ISRC1 status bits and PBs not valid ISRC1 status bits and PBs valid. 0xC8—[2:0], ISRC Status These bits define where in the ISRC track the samples are. At ...
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... Any base address higher than the maximum value does not produce an acknowledge signal. Data are read from the control registers of the AD9393 in a similar manner. Reading requires two data transfer operations: • The base address must be written with the R/W bit of the slave address byte low to set up a sequential read operation. • ...
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... AD9393 SERIAL INTERFACE READ/WRITE EXAMPLES Write to one control register: 1. Start signal Slave address byte (R/ W bit = low Base address byte 4. Data byte to base address 5. Stop signal Write to four consecutive control registers: 1. Start signal Slave address byte (R/ W bit = low ...
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... EMI, and reduce the current spikes inside the AD9393. If series resistors are used, place them as close as possible to the AD9393 pins (although try not to add vias or extra length to the output trace to move the resistors closer). If possible, limit the capacitance that each of the digital outputs drives to less than 10 pF ...
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... AD9393 COLOR SPACE CONVERTER (CSC) COMMON SETTINGS HDTV YCRCB (0 TO 255) TO RGB (0 TO 255) (DEFAULT SETTING FOR AD9393) Table 29. Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x0C 0x52 Table 30. Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x1C 0x54 Table 31. Register Blue/Cb Coeff 1 ...
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... Green/Y Coeff 3 0x3F 0x40 0x41 0x09 0xD3 0x00 Blue/Cb Coeff 2 Blue/Cb Coeff 3 0x47 0x48 0x49 0x1A 0x96 0x07 Rev Page AD9393 Red/Cr Offset 0x3A 0x3B 0x3C 0x00 0x1C 0x84 Green/Y Offset 0x42 0x43 0x44 0x6F 0x02 0x1E Blue/Cb Offset 0x4A ...
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... AD9393 RGB (0 TO 255) TO SDTV YCRCB (0 TO 255) Table 47. Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x08 0x2D Table 48. Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x04 0xC9 Table 49. Register Blue/Cb Coeff 1 Address 0x45 0x46 Value 0x1D 0x3F RGB (0 TO 255) TO SDTV YCRCB (16 TO 235) Table 50 ...
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... Chip Scale Package Pin Grid Array (CSP_BGA) −10°C to +80°C 76-Pin Chip Scale Package Pin Grid Array (CSP_BGA) Evaluation Board Rev Page CORNER INDEX AREA 0.65 MIN COPLANARITY 0.08 MAX SEATING PLANE Package Option BC-76-2 BC-76-2 AD9393 ...
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... AD9393 NOTES Rev Page ...
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... NOTES Rev Page AD9393 ...
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... AD9393 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08043-0-10/09(0) Rev Page ...