WM8734 ETC-unknow, WM8734 Datasheet - Page 20

• Manufacturer Part Number: WM8734
• Description: Stereo Audio Codec
• Manufacturer: ETC-unknow

WM8734
Figure 18 Right Justified Mode
Figure 19 DSP Mode
w
Note: Input word length is defined by the IWL register, LRP = 1
DACLRC/
ADCLRC
DACLRC/
ADCLRC
DACDAT/
DACDAT/
ADCDAT
ADCDAT
BCLK
BCLK
MSB
1 BCLK
1
2
DSP mode is where the left channel MSB is available on either the 1
(selectable by LRP) following a LRC transition high. Right channel data immediately follows left
channel data.
In all modes DACLRC and ADCLRC must always change on the falling edge of BCLK, refer to Figure
16, Figure 17, Figure 18 and Figure 19. Operating the digital audio interface in DSP mode allows
ease of use for supporting the various sample rates and word lengths. The only requirement is that
all data is transferred within the correct number of BCLK cycles to suit the chosen word length.
In order for the digital audio interface to offer similar support in the three other modes (Left Justified,
I
ratios need more careful consideration.
In Slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio.
BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for
each DACLRC/ADCLRC transition to clock the chosen data word length.
2
3
S and Right Justified), the DACLRC, ADCLRC and BCLK frequencies, continuity and mark-space
MSB
Input Word Length (IWL)
LEFT CHANNEL
1
LEFT CHANNEL
2
3
n-2 n-1
LSB
n
n-2 n-1
1
2
3
1/fs
RIGHT CHANNEL
n
LSB
1/fs
MSB
n-2 n-1
1
RIGHT CHANNEL
2
n
3
st
or 2
AI Rev 2.2 November 2001
Advanced Information
nd
n-2 n-1
rising edge of BCLK
n
LSB
20