ADT7468 Analog Devices, Inc., ADT7468 Datasheet - Page 35

• Manufacturer Part Number: ADT7468
• Description: Dbcool Remote Thermal Controller And Voltage Monitor
• Manufacturer: Analog Devices, Inc.

MISCELLANEOUS FUNCTIONS
OPERATING FROM 3.3 V STANDBY
The ADT7468 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor is lowered in these states. If
using the dynamic T
processor changes the CPU temperature and changes the
dynamics of the system under dynamic T
when monitoring THERM , the THERM timer should be
disabled during these states.
Dynamic T
<1> VCCPLO = 1
When the power is supplied from 3.3 V STBY and the V
voltage drops below the V
1.
2.
3.
4.
5.
Once the core voltage, V
everything is re-enabled and the system resumes normal
operation.
XNOR TREE TEST MODE
The ADT7468 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying a stimulus to the pins included in the XNOR tree, it is
possible to detect opens or shorts on the system board.
The XNOR tree test is invoked by setting Bit 0 (XEN) of the
XNOR tree test enable register (Reg. 0x6F).
Figure 47 shows the signals that are exercised in the XNOR tree
test mode.
Status Bit 1 (V
SMBALERT is generated, if enabled.
THERM monitoring is disabled. The THERM timer
should hold its value prior to the S3 or S5 state.
Dynamic T
being adjusted due to an S3 or S5 state.
The ADT7468 is prevented from entering the shutdown
state.
MIN
Control Register 1 (Reg. 0x36)
MIN
CCP
control is disabled. This prevents T
MIN
) in Status Register 1 is set.
mode, lowering the core voltage of the
CCP
CCP
, goes above the V
low limit, the following occurs:
MIN
control. Likewise,
CCP
low limit,
MIN
CCP
from
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POWER-ON DEFAULT
When the ADT7468 is powered up, it polls the V
If V
powered-up), then the ADT7468 assumes the functionality of
the default registers after the ADT7468 is addressed via any
valid SMBus transaction.
If V
up), then a fail-safe timer begins to count down. If the
ADT7468 is not addressed by any valid SMBus transaction
before the fail-safe timeout (4.6 s) lapses, then the ADT7468
drives the fans to full speed. If the ADT7468 is addressed by a
valid SMBus transaction after this point, the fans stop, and the
ADT7468 assumes its default settings and begins normal
operation.
If V
up), then a fail-safe timer begins to count down. If the
ADT7468 has been addressed by a valid SMBus transaction
before the fail-safe timeout (4.6 sec) lapsed, then the ADT7468
operates normally, assuming the functionality of all the default
registers. See the flow chart in Figure 48.
CCP
CCP
CCP
stays below 0.75 V (the system CPU power rail is not
goes high (the system processor power rail is powered
goes high (the system processor power rail is powered
TACH1
TACH2
TACH3
TACH4
PWM2
PWM3
VID0
VID1
VID2
VID3
VID4
Figure 47. XNOR Tree Test
PWM1/XTO
CCP
ADT7468
input.