FSLV16211 Fairchild Semiconductor, FSLV16211 Datasheet
FSLV16211
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FSLV16211 Summary of contents
Page 1
... Application Diagram © 2003 Fairchild Semiconductor Corporation FSLV16211 Rev. 1.0.1 Description The FSLV16211 is a 24-bit, high-speed, low-voltage bus switch. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. This device’s design allows this part to be used as a 12- bit or 24-bit bus switch ...
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... Connection Diagram Figure 2. Pin Assignments for TSSOP (Top Through View) Figure 3. Pin Assignments for FBGA (Top Through View) © 2003 Fairchild Semiconductor Corporation FSLV16211 Rev. 1.0.1 Pin Description Pin Name 1A FBGA Pin Assignments ...
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... Output Voltage OUT Input Rise and Fall Time Free Air Operating Temperature A Note: 2. Unused control inputs must be held HIGH or LOW. They may not float. © 2003 Fairchild Semiconductor Corporation FSLV16211 Rev. 1.0.1 Parameter (1) Parameter Switch Control Input Switch I/O 3 Min. Max. Unit -0.5 4.6 V -0.5 4 ...
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... This parameter is guaranteed by design, but is not production tested. The bus switch contributes no propagation delay other than the RC delay of the typical on resistance of the switch and the load capacitance, when driven by an ideal voltage source (zero output impedance). © 2003 Fairchild Semiconductor Corporation FSLV16211 Rev. 1.0.1 Conditions V CC ...
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... Input/Output Capacitance I/O Capacitance is characterized, but not production tested. AC Loading Waveforms Figure 4. AC Test Circuit Symbol MVO CCV © 2003 Fairchild Semiconductor Corporation FSLV16211 Rev. 1.0.1 Parameter Conditions V – 3. ,OE= 3.3V CC Figure 5. AC Waveforms V CC 3.3V ± 0.3V 1.5V 1.5V 0.3V 6.0V 3.0V 2ns 5 Min. ...
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... Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 6. 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide © 2003 Fairchild Semiconductor Corporation FSLV16211 Rev. 1.0.1 6 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters (inches) unless otherwise noted. Figure 7. 56-Lead Thin-Shrink Small Outline Package (TSSOP), JEDEC MO153, 6.1mm Wide © 2003 Fairchild Semiconductor Corporation FSLV16211 Rev. 1.0.1 7 www.fairchildsemi.com ...
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... Fairchild Semiconductor Corporation FSLV16211 Rev. 1.0.1 8 www.fairchildsemi.com ...