PIC16C774 Microchip Technology Inc., PIC16C774 Datasheet - Page 89

• Manufacturer Part Number: PIC16C774
• Description: 28/40-pin, 8-bit Cmos Microcontrollers W/ 12-bit A/d
• Manufacturer: Microchip Technology Inc.

8.2.15
Clock arbitration occurs when the master, during any
receive, transmit, or repeated start/stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the baud rate gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This
ensures that the SCL high time will always be at least
one BRG rollover count in the event that the clock is
held low by an external device
FIGURE 8-33: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
BRG overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and start count
to measure high time interval
1999 Microchip Technology Inc.
SCL
SDA
CLOCK ARBITRATION
T
BRG
(Figure
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
8-33).
T
Advance Information
BRG
SCL line sampled once every machine cycle (T
Hold off BRG until SCL is sampled high.
8.2.16
While in sleep mode, the I
addresses or data, and when an address match or
complete byte transfer occurs wake the processor from
sleep ( if the SSP interrupt is enabled).
8.2.17
A reset disables the SSP module and terminates the
current transfer.
SLEEP OPERATION
EFFECTS OF A RESET
T
SCL = 1 BRG starts counting
clock high interval.
BRG
PIC16C77X
2
C module can receive
osc
DS30275A-page 89
4).