AL4CS205 AverLogic Technologies Inc, AL4CS205 Datasheet - Page 2

• Manufacturer Part Number: AL4CS205
• Description: 256, 512, 1k, 2k, 4k X 18 Synchronous Fifos
• Manufacturer: AverLogic Technologies Inc

independently at a maximum speed of 133
MHz.
pointer
straightforward bus interface to serially
read/write memory that reduces inter-chip
design efforts. The AL4CS2x5 embedded
memory array and high performance process
technologies
functions (read skip, fixed and programmable
status flags.. etc.) offer flexible memory
management.
These FIFOs support up to 18bit input and
output data bus-width that is controlled by
separate clock and enable signals respectively.
The input data is acquired at each rising edge
of a free running write clock while a write
enable control pin is asserted. The output data
is available after each rising edge of a free
running read clock while a read enable and
output enable control pins are asserted. When
output enable (/OE) is LOW, the data output
bus is active. If /OE is HIGH, the output data
bus will be in a high-impedance. This signal
can control whether the data is going to be
skipped during the read operation.
The
programmable Almost Full/Almost Empty
flags are powerful functions that can help
A
The 18bit input and output ports operate
VER
L
OGIC
FIFO
WCLK
/WEN
The built-in address decoder and
managing
T
/RS
/LD
ECHNOLOGIES
Input data bus
Full/Empty,
with
Offset Regissers
Write Control
Write Pointer
Reset Logic
, I
circuits
extended
Buffer
Input
Logic
NC
.
TEL
Half-Full
AL4CS205/215/225/235/245 FIFO Block Diagram
: 1 408 361-0400
provide
controller
1024 x18, 2048 x18
256 x18, 512 x18
and
RAM ARRAY
a
4096 x18
e-mail: [e-mail]
controlling software to manipulate the FIFO
more easily or to do retransmit operation.
Multiple AL4CS2x5s can cascade to expand
the storage depth or provide a longer delay.
The FIFOs can be chained by looping connect
/WXO, /RXO pins of the first FIFO chip to
/WXI,
respectively and connect /WXO, /RXO pins of
last cascading chip to /WXI, /RXI pins of the
first FIFO chip. Expanding AL4CS2x5 data
bus width is also possible by using multiple
AL4CS2x5 chips in parallel.
These chips are available as a 64pin TQFP and
STQFP Package.
D
ISTRIBUTED BY
/RXI
Expansion Logic
Flag Logic
Read Control
Read Pointer
Output
Buffer
pins
Logic
:
Output data bus
of
/OE
URL: www.averlogic.com
successive
RCLK
/REN
/WXO
/RXO
/RXI
/WXI
/PAE
/EF
/HF
/FF
/PAF
April 5, 2002
chips