MT9VDDF3272G-40B Micron Semiconductor Products, MT9VDDF3272G-40B Datasheet
MT9VDDF3272G-40B
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MT9VDDF3272G-40B Summary of contents
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DDR SDRAM Registered DIMM MT9VDDF3272 – 256MB MT9VDDF6472 – 512MB For the latest data sheet, refer to Micron’s Web site: Features • 184-pin, dual in-line memory module (DIMM) • Fast data transfer rates: PC3200 • Utilizes 400 MT/s DDR SDRAM ...
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... Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing Table 2: Part Numbers and Timing Parameters Part Number Module Density MT9VDDF3272G-40B__ 256MB 256MB MT9VDDF3272Y-40B__ MT9VDDF6472G-40B__ 512MB MT9VDDF6472Y-40B__ 512MB Note: All part numbers end with a two-place code (not shown), designating component and PCB revisions ...
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Table of Contents Features 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 184-Pin DIMM (MO-206 ...
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List of Tables Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Pin Assignments and Descriptions Table 3: Pin Assignment 184-Pin DIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ17 47 REF 2 DQ0 25 DQS2 ...
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Table 4: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information Pin Numbers Symbol 10 RESET# 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21 157 52, ...
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Table 4: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 6 for more information Pin Numbers Symbol 12,13, 19, 20, DQ0–DQ63 23, 24, 28, 31, 33, 35, 39, ...
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Figure 3: Functional Block Diagram – Low-Profile PCB RS0# DQS0 DM0 DQS1 DM1 DQS2 DM2 DQS3 DM3 DQS8 DM8 U6, U7 S0# BA0, BA1 A0-A12 RAS# CAS# CKE0 WE# CK CK# Notes: 1. Unless otherwise noted, resistor values are 22Ω. ...
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Figure 4: Functional Block Diagram – Very Low-Profile PCB RS0# DQS0 DM0 DQS1 DM1 DQS2 DM2 DQS3 DM3 DQS8 DM8 U6, U13 R S0# E BA0, BA1 G A0-A12 I RAS# S CAS# T CKE0 E WE ...
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General Description The MT9VDDF3272 and MT9VDDF6472 are high-speed, CMOS, dynamic random- access, 256MB and 512MB memory modules organized in x72 (ECC) configuration. DDR SDRAM modules uss internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate ...
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SDRAM organizations and timing parameters. The remaining 128 bytes of stor- age are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I bus ...
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Figure 5: Mode Register Definition Diagram BA1 M14 and M13 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23 DDAF9C32_64x72_2.fm - Rev. C 7/05 ...
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Table 5: Burst Definition Table Burst Length Notes: 1. For a burst length of two, A1–Ai select the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2–Ai select the four-data-element block; ...
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Figure 6: CAS Latency Diagram COMMAND COMMAND COMMAND Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ com- mand and the availability of the first bit of output data. The latency can ...
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Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7–A12 each set to zero, and bits A0–A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER ...
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Figure 7: Extended Mode Register Definition Diagram BA1 BA0 E12 E11 0 0 – – Notes: 1. BA1 and BA0 (E14 and E13) must be “0, 1” to select the Extended Mode Register (vs. the base Mode ...
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Commands Table 7, Commands Truth Table, and Table 8, DM Operation Truth Table, provide a gen- eral reference of available commands. For a more detailed description of commands and operations, refer to the 256Mb or 512Mb DDR SDRAM component data ...
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Absolute Maximum Ratings Stresses greater than those listed under “Absolute Maximum Ratings” may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those ...
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Table 11: IDD Specifications and Conditions – 256MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 24–27; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge (MIN); DQ, ...
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Table 12: IDD Specifications and Conditions – 512MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 24–27; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge (MIN); DQ, ...
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Table 13: Capacitance Note: 11; notes appear on pages 24–27 Parameter Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 14: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: ...
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Table 14: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 8, 10, 12; notes appear on pages 24–27; 0°C ≤ Characteristics Parameter DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: Output ...
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HZ and tions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The Don’t Care state after completion of the postamble ...
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Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +300mV (2.9V max), whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not ...
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The voltage levels used are derived from a minimum V load. In practice, the voltage levels obtained from a properly terminated bus will pro- vide significantly different voltage values. 35 not be greater than 1/3 of the ...
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Initialization To ensure device operation the DRAM must be initialized as described below: 1. Simultaneously apply power Apply V 3. Assert and hold CKE at a LVCMOS logic low. 4. Provide stable CLOCK signals. 5. Wait at ...
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Figure 10: Initialization Flow Diagram Step pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23 DDAF9C32_64x72_2.fm - Rev. C 7/05 EN 256MB, 512MB: (x72, ...
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Register and PLL Specifications Table 15: Register Timing Requirements and Switching Characteristics Note: 1 Register Symbol Paramerter f Clock Frequency clock t Clock to Output Time pd t Reset to Output Time PHL t Pulse Duration w SSTL (bit pattern ...
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Table 16: PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 Parameter Symbol Operating Clock Frequency Input Duty Cycle Stabilization Time Cycle to Cycle Jitter Static Phase Offset Output Clock Skew Period Jitter t Half-Period Jitter Input Clock Slew ...
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Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figure 11, Data Validity, and Figure 12, ...
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Figure 12: Definition of Start and Stop SCL SDA Figure 13: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver pdf: 09005aef80f6ab6a, source: 09005aef80f6ab23 DDAF9C32_64x72_2.fm - Rev. C 7/05 EN 256MB, 512MB: (x72, ECC, ...
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Table 17: EEPROM Device Select Code The most significant bit (b7) is sent first Select Code Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes Mode Current Address Read Random Address Read Sequential Read ...
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Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Output Low Voltage 3mA OUT Input Leakage Current: ...
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Table 21: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte Description 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Row Addresses ...
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Table 21: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte Description 46 Reserved 47 DIMM Height 48–61 Reserved 62 SPD Revision 63 Checksum For Bytes 0-62 64 Manufacturer’s JEDEC ID Code 65-71 Manufacturer’s JEDEC ID Code ...
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Package Dimensions Figure 15: 184-PIN DIMM DDR Modules – Low-Profile 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.050 (1.27) TYP. 0.091 (2.30) 2.55 (64.77) TYP. PIN 184 Figure 16: 184-PIN DIMM ...
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Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and ...