MT9VDDT6472HY-40B Micron Semiconductor Products, MT9VDDT6472HY-40B Datasheet
MT9VDDT6472HY-40B
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MT9VDDT6472HY-40B Summary of contents
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DDR SDRAM SMALL-OUTLINE DIMM Features • 200-pin, small-outline, dual in-line memory module (SODIMM) • Supports ECC error detection and correction • Fast data transfer rates: PC3200 • Utilizes 400 MT/s DDR SDRAM components • 256MB (32 Meg x 72), 512MB ...
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Table 2: Part Numbers and Timing Parameters MODULE PART NUMBER DENSITY MT9VDDT3272H(I)G-40B__ MT9VDDT3272H(I)Y-40B__ MT9VDDT6472H(I)G-40B__ MT9VDDT6472H(I)Y-40B__ MT9VDDT12872H(I)G-40B__ MT9VDDT12872H(I)Y-40B__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: ...
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Table 3: Pin Assignment (200-Pin SODIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 101 REF DQ19 103 SS 5 DQ0 55 DQ24 105 7 DQ1 57 V 107 DD 9 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS SYMBOL 118, 119, 120 WE#, CAS#, RAS# 35, 37, 89, 91, 158, 160 CK0, CK0#, CK1, ...
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Table 5: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS SYMBOL 195 194, 196, 198 SA0–SA2 193 1, 2 9-10, 21-22, 33-34, 36, 45- 46, ...
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S0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 ...
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General Description The MT9VDDT3272H, MT9VDDT6472H, MT9VDDT12872H, are high-speed CMOS, dynamic random-access, 256MB, 512MB, and 1GB memory modules organized in x72 (ECC) configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate ...
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Burst Length Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being program- mable, as shown in Mode Register Diagram. The burst length determines the maximum number of column locations that can be accessed ...
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Table 6: Burst Definition Table ORDER OF ACCESSES WITHIN STARTING BURST COLUMN TYPE = LENGTH ADDRESS SEQUENTIAL 0-1-2 1-2-3 2-3-0 3-0-1 ...
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Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and out- put drive strength. These functions are controlled via the bits shown in Figure 6, Extended Mode ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 256MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 46; notes appear on pages 18–20; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN ...
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Table 13: I Specifications and Conditions – 512MB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 46; notes appear on pages 18–20; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 14: I Specifications and Conditions – 1GB DD DDR SDRAM components only Notes: 1–5, 8, 10, 12, 46; notes appear on pages 18–20; 0°C ≤ T PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–5, 12-15, 28; notes appear on pages 18–20; 0°C ≤ CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock ...
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Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12-15, 28; notes appear on pages 18–20; 0°C ≤ CHARACTERISTICS PARAMETER DQS write postamble Write recovery time Internal WRITE to READ command delay ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The data valid window is derived by achieving t t other specifications CK/2 ...
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Figure 7: Pull-Down Characteristics 160 140 120 100 0.0 0.5 1 (V) (V) OUT OUT 38. During initialization equal to or less than may be ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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Figure 10: Component Case Temperature vs. Air Flow 100 NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across all modules. 2. The component case temperature ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure ...
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Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 18: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read Sequential ...
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Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 21: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Row Addresses ...
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Table 21: Serial Presence-Detect Matrix (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 29 Minimum RAS# to CAS# Delay, 30 Minimum RAS# Pulse Width, 31 Module Rank Density 32 Address And Command Setup Time, 33 Address And ...
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Figure 15: 200-PIN DDR SODIMM Dimensions 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (0.99) U6 PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation Advance: This datasheet contains initial ...