IR1110 International Rectifier Corp., IR1110 Datasheet - Page 19

• Manufacturer Part Number: IR1110
• Description: Soft Start Controller Ic In A 64-lead Mqfp Package
• Manufacturer: International Rectifier Corp.

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Wave Intersect Comparator goes high, which occurs when the line voltage returns to normal. Q2
is momentarily turned ON, allowing the voltage on C
the Ramp, and Q5 is turned OFF, unclamping C
disconnected from ground, allowing C
Voltage Dip during Dynamic Regulation
voltage that will set the Voltage Dip Comparator and cause the bus voltage to undershoot.
parator remains high, and the Voltage Dip Comparator will be quickly reset, ramping the bus
voltage back to the set value.
a rate that does not significantly “overtake” the discharge rate of C
R
Undervoltage and Undervoltage Lockout Comparators
reference value.
nominal value of about 1.5V. C
either comparator is low, the SCR firing pulses are inhibited, and Q4 is turned OFF, clamping
the ramp.
One Phase Loss Circuit
input phase is missing. With 1-phase shutdown enabled, each 1-phase loss pulse discharges
C
output of the UV Lockout Comparator goes low.
pulses are generated;
from the zero crossing of the line voltage
reinforces the ramp clamp function. Under condition (c) it results in automatic limiting of short
circuit current, as explained later.
(a) during one phase loss
(b) briefly during abnormal dips of line voltage
(c) if the DC bus is short circuited and the SCR firing angle is advanced by more than about 30
DIP1
UVLO
and R
by about 1.5V. During the third successive pulse, C
After the above delay, the Voltage Dip Comparator is reset when the output of the Timing
When the output of the Voltage Dip Comparator is low, Q1 is turned OFF. R
If |V
Since the timing waves are still present, the output of the Timing Wave Intersect Com-
This undershoot of the bus voltage will be avoided if changes in |V
The UV Comparator delivers a high output when V
The UV Lockout Comparator delivers a high output when the voltage C
The outputs of the UV and UV Lockout Comparators are ANDed. When the output of
A train of fixed duration (nominal 2msec) pulses are delivered to the gate of Q6, if one
The principle of generation of the 1-phase loss pulses is illustrated in Figure 8. These
With 1-phase shutdown enabled, generation of “1-phase loss” pulses under condition (b)
The 1-phase loss pulses at 1PHLED output follow the output of the 1-Phase Loss Circuit.
DIP2
BREF
.
| is rapidly decreased by a sufficient amount, this may cause a decrease of bus
UVLO
ADVANCE INFORMATION
is driven from a current source of approximately 2uA.
PK
to hold its charge during the voltage dip.
ERR
. Ramp-back of the bus voltage now occurs.
HOLD
to reset. Q4 is turned ON, unclamping
UVLO
DD
is discharged sufficiently that the
exceeds the internally fixed
HOLD
, which is set by C
BUSREF
UVLO
| are controlled at
PKD
exceeds a
IR1110
is then
HOLD
,
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