FIN24C Fairchild Semiconductor, FIN24C Datasheet

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... TM ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 General Description The FIN24C µSerDes™ low-power Serializer/ Deserializer (SerDes) that can help minimize the cost and power of transferring wide signal paths. Through the use of serialization, the number of signals transferred from one point to another can be significantly reduced. ...

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... Functional Block Diagram CKREF STROBE DP[m+1:24] DP[1:m] Note: I Control CKP S1 S2 DIRI ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Word PLL 0 Boundary Generator I cksint Serializer Control Serializer oe Deserializer Deserializer cksint Control WORD CK Generator Control Logic DIRO Freq. Direction Control Control oe Power Down Control Figure 1 ...

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... The DSO/DSI serial port terminals have been arranged such that when one device is rotated 180° to the other device, the serial connections properly align without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Number of Terminals 20 ...

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... Connection Diagrams Figure 2. Terminal Assignments for MLP (Top View (Top View) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 DP[9] 1 DP[10] 2 DP[11] 3 DP[12 DDP CKP 6 DP[13] 7 DP[14] 8 DP[15] 9 DP[16] 10 Pin Assignments DP[9] DP[7] DP[5] B DP[11] DP[10] DP[6] C CKP DP[12] DP[8] D DP[13] DP[14] V DDP E DP[15] DP[16] GND F DP[17] DP[18] DP[21] J DP[19] DP[20] DP[22] Figure 3. Terminal Assignments for µBGA ...

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... Control Logic Circuitry The FIN24C has four signals that are selectable as two unidirectional inputs and two unidirectional outputs four unidirectional inputs or four unidirectional outputs. These are often used by applications for control signals. The mode signals S1 and S2 determine the direction of the DP[21:24] data signals. The 00 state provides for a power-down state where all functionality of the device is disabled or reset ...

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... When operating in a 2-bit control mode, serialized bits 21 and 22 appear on outputs 23 and 24 of the deserializer. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Power-Down Mode: (Mode 0) Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a ...

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... No Data Figure 5. Serializer Timing Diagram (CKREF does not equal STROBE) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 The Phase-Locked Loop (PLL) must receive a stable CKREF signal to achieve lock prior to any valid data being sent. The CKREF signal can be used as the data STROBE signal, provided that data can be ignored during the PLL lock phase. ...

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... CKS0 No Data Figure 6. Serializer Timing Diagram Using Provided Bit Clock (No CKREF) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (Continued) A third method of serialization can be accomplished with a free running bit clock on the CKSI signal. This mode is enabled by grounding the CKREF signal and driving the DIRI signal HIGH. ...

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... WORD n-2 Figure 8. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 When the DIRI signal is asserted LOW, the device is configured as a deserializer. Data is captured on the serial port and deserialized through use of the bit clock sent with the data ...

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... Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 bidirectional pins should be connected to GND through a high-value resistor FIN24C devices is configured as an unidirectional serializer, unused data I/O can be treated as unused inputs. If the FIN24C is hardwired as a deserializer, unused date I/O can be treated as unused outputs. Deserializer To Serializer ...

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... DS signals source synchronous with CKSO. 5. Generates an embedded word clock for each strobe signal. ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Mode 0 state ( upon detecting a LOW on both the S1 and S2 signals. Any of the other modes are DS+ entered by asserting either HIGH and by pro- DS- viding a CKREF signal ...

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... Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. ■ Do not place test points on differential serial wires. ■ Use differential serial wires a minimum of 2cm away from the antenna. ■ ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 FIN24C CKREF CKSO CKSI STROBE DS ...

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... All Pins CKSO, CKSI, DSO to GND Recommended Operating Conditions Symbol Supply Voltage DDA DDS V Supply Voltage DDP T Operating Temperature A V Supply Noise Voltage DDA-PP ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Parameter Parameter 13 Min. Max. Unit -0.5 +4.6 V -0.5 +4.6 V Continuous -65 +150 °C +150 °C +260 ° ...

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... Voltage is referenced to GROUND unless otherwise specified (except ΔV and the difference in device ground levels between the CTL driver and the CTL receiver. GO ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Test Conditions I = –2 3.3 ± 0.3 OH DDP V = 2.5 ± 0.2 DDP V = 1.8 ± ...

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... DD_SER2 DDA DDS ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Test Conditions All DPI and Control Inputs CKREF DIRI = 1 All DPI and Control Inputs CKREF DIRI = 1 All DPI and Control Inputs CKREF DIRI = 1 ...

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... Output Rise Time ROLH (20% to 80%) t Output Fall Time ROHL (80% to 20%) ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 Test Conditions See Figure 20 CKREF does not equal STROBE See Figure 20 See Figure 20 CKREF x 26 DIRI = 1, See Figure 5MHz) CKREF Does Not Equal STROBE ...

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... CKREF, STROBE, S1, S2, DIRI C Capacitance of Parallel Port Pins IO DP[1:12] C Capacitance of Differential I/O Signals IO-DIFF ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 = 2.775V and T = 25°C. Positive current values refer to the current flowing into Test Conditions DIRI LOW-to-HIGH or HIGH-to-LOW DIRI LOW-to-HIGH ...

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... Typical values are measured 2.775V TLH 80% 20% V DIFF V = (DS+) – (DS-) DIFF DS – DS- Figure 17. CTL Output Load and Transition Times ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 DS+ DUT DS- Figure 15. CTL Input Common Mode Test Circuit T 999h b b ...

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... Figure 21. Deserializer Data Valid Window Time and Clock Output Parameters t TCCD STROBE V DD/2 CKS0- V DIFF CKS0+ Note: STROBE = CKREF Figure 23. Serializer Clock Propagation Delay ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (Continued) Data t HTC t PDV 50% 25% t RCOL CKSI CKSI+ Figure 24. Deserializer Clock Propagation Delay ...

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... PLZ(HZ DS+,CKS0+ HIGH-Z DS-,CKS0- Note: CKREF must be active and PLL must be stable. Figure 29. Serializer Enable and Disable Time ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (Continued) CKSO- t H_DS CKSO+ DSO+ DSO- Note: Data is typically edge aligned with the clock. Figure 26. Differential Output Signal Skew ...

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... Sketch A (Side or Front Sectional View) Component Rotation Shipping Reel Dimension Dia A max Tape Dia A Dim B Width Max. Min. 8 330 1.5 12 330 1.5 16 330 1.5 ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0 Min. ±0.1 ±0.1 ±0.1 Typ ...

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... Sketch A (Side or Front Sectional View) Component Rotation Shipping Reel Dimension Dia A max Tape Dia A Dim B Width Max. Min. 8 330 1.5 12 330 1.5 16 330 1.5 ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (Continued Min. ±0.1 ±0.1 ± ...

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... Dimensions are in millimeters unless otherwise noted. 2X 0.10 C TERMINAL A1 CORNER INDEX AREA (QA CONTROL VALUE) 1.00 MAX 0. SEATING PLANE Figure 31. Pb-Free, 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 3.50 2X 0.10 C (0.6) 4.50 0.5 0.89±0.082 0.45±0.05 0.21±0.04 0.23±0.05 23 (0.35) (0.5) 2 ...

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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 32. Pb-Free, 40-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 (DATUM A) 24 www.fairchildsemi.com ...

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... PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary No Identification Needed Obsolete ©2005 Fairchild Semiconductor Corporation FIN24C Rev. 1.0.2 OCX™ SILENT SWITCHER OCXPro™ SMART START™ ® OPTOLOGIC SPM™ OPTOPLANAR™ ...