NCP1230 ON Semiconductor, NCP1230 Datasheet - Page 13
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NCP1230
Manufacturer Part Number
NCP1230
Description
Fixed Frequency Controller Featuring Pfc Go To Standby Function
Manufacturer
ON Semiconductor
Datasheet
1.NCP1230.pdf
(21 pages)
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NCP1230 confirms that the low output power condition is
present, and the internal SW1 opens, and the PFC_Vcc
signal output is shuts down. While the NCP1230 is in the
skip mode the FB pin will move around the 750 mV
threshold level, with approximately 100 mVp−p of
hysteresis on the skip comparator, at a period which depends
upon the (light) loading of the power supply and its various
time constants. Since this ripple amplitude superimposed
over the FB pin is lower than the second threshold (1.25
volt), the PFC_Vcc comparator output stays high (PFC_Vcc
output Pin 1 is low).
and the feedback voltage rises above the 1.25 volts
threshold, the NCP1230 exits the skip mode, and returns to
normal operation.
Leaving Standby (Skip Mode)
reference (leaving standby) the skip cycle activity stops and
SW1 immediately closes and restarts the PFC, there is no
delay in turning on SW1 under these conditions, refer to
Figure 32.
Current Sense
the current sense input is internally clamped to 1.0 V, so the
sense resister is determined by Rsense = 1.0 V /Ipk
maximum.
end of the 18k resistor is connect to the output of the internal
oscillator for ramp compensation (refer to Figure 33).
Max I
1.25 V
0.75 V
V
In Phase four, the output power demands have increases
When the feedback voltage rises above the 1.25 volts
The NCP1230 is a peak current mode controller, where
There is a 18k resistor connected to the CS pin, the other
FB
P
PFC is Off
Regulation
PFC is On
Figure 32.
Skip + 60%
PFC is Off
125 ms
Delay
No Delay
PFC is On
http://onsemi.com
13
Ramp Compensation
Conduction Mode (CCM) with a duty−cycle greater than
50%, oscillation will take place at half the switching
frequency. To eliminate this condition, Ramp Compensation
can be added to the current sense signal to cure sub harmonic
oscillations. To lower the current loop gain one typically
injects between 50 and 100% of the inductor down slope.
is summed internally through a 18 kW resistor to the current
sense pin. To implement ramp compensation a resistor needs
to be connected from the current sense resistor, to the current
sense pin 3.
Example:
NCP1230, at 65 kHz the dv/dt of the ramp is 130 mV/ms.
Assuming we are designing a FLYBACK converter which
has a primary inductance, Lp, of 350 mH, and the SMPS has
a +12 V output with a Np:Ns ratio of 1:0.1. The OFF time
primary current slope is given by:
when imposed on a current sense resistor (Rsense) of 0.1 W.
If we select 75% of the inductor current downslope as our
required amount of ramp compensation, then we shall inject
27 mV/ms.
divider ratio (divratio) between Rcomp and the 18 kW is
0.207. Therefore:
In Switch Mode Power Supplies operating in Continuous
The NCP1230 provides an internal 2.3 Vpp ramp which
If we assume we are using the 65 kHz version of the
With our internal compensation being of 130 mV, the
+
−
(V out ) V f) @
Fb/3
R comp + 18k @ divratio
L p
LEB
Np
Ns
(1 * divratio)
Figure 33.
= 371 mA/ms or 37 mV/ms
18 k
CS
= 4.69 kW
Rcomp
2.3 V
0V
Rsense