RS5C348A RICOH Co.,Ltd., RS5C348A Datasheet - Page 14

• Manufacturer Part Number: RS5C348A
• Description: 4-wire Serial Interface Real-time Clock
• Manufacturer: RICOH Co.,Ltd.

Rx5C348A/B
Rev.2.01
(1) VDSL
(2) VDET
(3) SCRATCH1
(4) XSTP
D7
VDSL
VDSL
0
Control Register 2 (Address Fh)
12345
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. or
Pulse Mode: The “L” period of output pulses will increment or decrement by a maximum of ±3.784 ms. For
Level Mode: A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784 ms.
*) Default settings: Default value means read / written values when the XSTP bit is set to “1” due to VDD
The VDSL bit is intended to select the VDD supply voltage monitoring threshold settings.
Once the VDET bit is set to 1, the supply voltage monitoring circuit will be disabled while the VDET bit will
hold the setting of 1.
monitoring circuit. Conversely, setting the VDET bit to 1 causes no event.
This bit is intended for scratching and accepts the reading and writing of 0 and 1. The SCRATCH1 bit will
be set to 0 when the XSTP bit is set to 1 in Control Register 2.
The XSTP bit is for sensing a halt in the oscillation of the crystal oscillator. Oscillation Halt sensing circuit
operates only when CE pin is Low.
* The XSTP bit will be set to 1 once a halt in the oscillation of the crystal oscillator is caused by such events
as power-on from 0 volts and a drop in supply voltage. The XSTP bit will hold the setting of 1 even after the
XSTP
VDSL
0
1
VDET
0
1
SCRATCH1
0
1
0
1
60sec. as follows:
D6
VDET
VDET
0
/INTR Pin
CTFG Bit
example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.
(Increment of
second counter)
D5
SCRA
TCH1
SCRA
TCH1
0
Description
Description
Description
Selecting the VDD supply voltage monitoring threshold setting of
2.1v.
Selecting the VDD supply voltage monitoring threshold setting of
1.6v.
Indicating supply voltage above the supply voltage monitoring
threshold settings.
Indicating supply voltage below the supply voltage monitoring
threshold settings.
Description
VDD Supply Voltage Monitoring Threshold Selection Bit
Supply Voltage Monitoring Result Indication Bit
Scratch Bit 1
Oscillation Halt Sensing Bit
Sensing a normal condition of oscillation
Sensing a halt of oscillation
power-on from 0v or oscillation stopping
The VDET bit accepts only the writing of 0, which restarts the supply voltage
Setting CTFG bit to 0
D4
XSTP
XSTP
1
(Increment of
second counter)
/CLEN1
/CLEN1
D3
0
D2
CTFG
CTFG
0
- 14 -
(Increment of
second counter)
WAFG
WAFG
D1
0
Setting CTFG bit to 0
D0
DAFG
DAFG
0
(For Writing)
Default Settings *)
(For Reading)
(Default)
(Default)
(Default)
(Default)