HT46R321 Holtek Semiconductor Inc., HT46R321 Datasheet
HT46R321
Related parts for HT46R321
HT46R321 Summary of contents
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... Integrated PFD function for sound generation Power-down and wake-up functions reduce power consumption General Description The HT46R321 is 8-bit, high performance, RISC archi- tecture microcontroller devices. With their fully inte- grated A/D converter they are especially suitable for applications which interface to analog signals, such as those from sensors ...
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... Block Diagram Rev. 1.00 2 HT46R321 August 3, 2007 ...
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... Positive power supply Negative power supply, ground. OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the sys- tem clock at 1/4 frequency. 3 HT46R321 August 3, 2007 ...
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... DD V =0. =0. =0. =0. =0. =0. =0. HT46R321 Typ. Max. Unit 5.5 V 5.5 V 0.6 1.5 mA 2.0 4.0 mA 0.8 1.5 mA 2 3.0 3 ...
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... Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 0 3.3V~5. Wake-up from HALT 0. HT46R321 Typ. Max. Unit 0 1 2.5 12 Bits Ta=25 C Typ. Max. Unit 4000 kHz 8000 kHz 4000 kHz 8000 kHz 90 180 s 65 ...
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... Gain Band Width Rev. 1.00 Test Conditions Min. V Conditions Calibration =0~V 1. Input overdrive= 10mV 60 No load R =1M, C =100p HT46R321 Ta=25 C Typ. Max. Unit 100 kHz August 3, 2007 ...
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... Program Counter Program Counter S10~S0: Stack register bits @7~@0: PCL bits 7 HT46R321 * ...
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... If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack Table Location * Table Location P10~P8: Current program counter bits 8 HT46R321 * August 3, 2007 ...
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... Logic operations - AND, OR, XOR, CPL Rev. 1.00 Rotation - RL, RR, RLC, RRC Increment and Decrement - INC, DEC Branch decision - SZ, SNZ, SIZ, SDZ .... The ALU not only saves the results of a data operation but also changes the status register. RAM Mapping 9 HT46R321 August 3, 2007 ...
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... If the stack is full, the interrupt re- quest will not be acknowledged, even if the related inter- rupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be pre- vented from becoming full. Function Status (0AH) Register Function INTC (0BH) Register 10 HT46R321 August 3, 2007 ...
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... Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required, If the oscillating fre- quency is less than 1MHz. System Oscillator 11 HT46R321 Priority Vector 1 004H 2 008H 3 ...
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... awakening from an interrupt, two sequences may happen. If the related interrupt is dis- abled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regu- Watchdog Timer 12 HT46R321 August 3, 2007 ...
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... Input mode Stack Pointer Points to the top of the stack Reset Timing Chart Reset Circuit Note: Most applications can use the Basic Reset Circuit as shown, however for applications with extensive noise recommended to use the Hi-noise Reset Circuit. Reset Configuration 13 HT46R321 August 3, 2007 ...
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... HT46R321 RES Reset WDT Times-out (HALT) (HALT)* 1uuu uuuu 1uuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu ...
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... PFD (Pro- grammable Frequency Divider) output by options. When the PFD function is selected, executing SET [PA].3 in- struction to enable PFD output and executing CLR [PA].3 instruction to disable PFD output. Function SYS /2 SYS /4 SYS /8 SYS /16 SYS /32 SYS /64 SYS /128 SYS TMRC (0EH) Register 15 HT46R321 August 3, 2007 ...
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... T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PDC) to control the input/output configuration. With this Input/Output Ports 16 HT46R321 August 3, 2007 ...
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... PWM1. The frequency source of the PWM counter co- mes from f . The PWM register is an eight bit register. SYS Once PD0/PD1 are selected as PWM outputs and the output function of PD0/PD1 is enabled (PDC. 6+2 PWM Mode 17 HT46R321 I/P O/P (PFD) (PFD) Logical PFD Input (Timer on) ...
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... Bit1 and bit0 of the ACSR register are used to select the A/D clock source. When the A/D conversion has completed, the A/D inter- rupt request flag will be set. The EOCB bit is set to 1 when the START bit is set from HT46R321 LED Driver August 3, 2007 ...
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... For internal test only. Rev. 1.00 Bit5 Bit4 Bit3 Bit2 ADRL (20H), ADRH (21H) Register Function ADCR (22H) Register Undefined, can t be used A/D Channel Function /8 ACSR (23H) Register 19 HT46R321 Bit1 Bit0 Channel AN0 AN1 AN2 AN3 AN4 AN5 August 3, 2007 ...
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... PB5 PB4 AN3 AN2 PB5 AN4 AN3 AN2 AN5 AN4 AN3 AN2 Port B, Port C Configuration /8 as the A/D clock SYS /8 as the A/D clock SYS 20 HT46R321 PB1 PB0 PB1 AN0 AN1 AN0 AN1 AN0 AN1 AN0 AN1 AN0 AN1 AN0 August 3, 2007 ...
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... START set START ; reset A/D clr START ; start A EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.00 A/D Conversion Timing 21 HT46R321 August 3, 2007 ...
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... Set the ARS bit to select which input pin is the reference voltage - closes either switch Adjust bits AOF0~AOF3 until the output status OPAOP has changed. Set AOFM=0 to select the normal operating mode 22 HT46R321 and V is shown below. DD LVR delay enter the ...
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... System oscillator crystal 5 Pull-high resistors (PA, PB, PD): none or pull-high 6 PWM enable or disable 7 PA0~PA7 wake-up: enable or disable 8 PFD enable or disable 9 Low voltage reset selection: enable or disable LVR function. 10 Comparator or OP selection 11 PCK or I/O Rev. 1.00 Function OPAC (1FH) Register Options /4) SYS 23 HT46R321 August 3, 2007 ...
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... RES pin reaches a high level. Ensure that the length of the wiring connected to the RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to Application Note HA0075E for more information. Rev. 1.00 24 HT46R321 August 3, 2007 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.00 Description 25 HT46R321 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 26 HT46R321 Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT46R321 August 3, 2007 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.00 PDF PDF PDF addr PDF PDF HT46R321 August 3, 2007 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT46R321 August 3, 2007 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.00 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT46R321 August 3, 2007 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.00 Program Counter+1 PDF PDF PDF addr PDF PDF HT46R321 August 3, 2007 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.00 PDF PDF Program Counter+1 PDF PDF PDF PDF HT46R321 August 3, 2007 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.00 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT46R321 August 3, 2007 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.00 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT46R321 August 3, 2007 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.00 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT46R321 August 3, 2007 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.00 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT46R321 August 3, 2007 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.00 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT46R321 August 3, 2007 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT46R321 August 3, 2007 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.00 PDF PDF PDF HT46R321 August 3, 2007 ...
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... Package Information 28-pin SKDIP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 1375 278 125 125 16 50 100 295 330 0 40 HT46R321 Max. 1395 298 135 145 20 70 315 375 15 August 3, 2007 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 394 290 14 697 HT46R321 Max. 419 300 20 713 104 August 3, 2007 ...
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... SSOP (150mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 228 150 8 386 HT46R321 Max. 244 157 12 394 August 3, 2007 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 28S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 16.8+0.3 0.2 22.2 0.2 43 HT46R321 August 3, 2007 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 Dimensions 0.3 8 0.1 1.75 0.1 7.5 0.1 1.55+0.1 1.5+0.25 4 0.1 2 0.1 6.5 0.1 10.3 0.1 2.1 0.1 0.3 0.05 13.3 44 HT46R321 August 3, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 45 HT46R321 August 3, 2007 ...