HT46R322 Holtek Semiconductor Inc., HT46R322 Datasheet
HT46R322
Related parts for HT46R322
HT46R322 Summary of contents
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... Integrated PFD function for sound generation Power-down and wake-up functions reduce power consumption General Description The HT46R322 and HT46R342 are 8-bit, high perfor- mance, RISC architecture microcontroller devices. With their fully integrated A/D converter they are especially suitable for applications which interface to analog sig- nals, such as those from sensors ...
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... Block Diagram Rev. 1.20 HT46R322/HT46R342 2 July 11, 2007 ...
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... Positive power supply Negative power supply, ground. OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the sys- tem clock at 1/4 frequency. 3 HT46R322/HT46R342 July 11, 2007 ...
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... PC, PD) PC Ports Sink Current for LED I OL2 Driver PE Ports Source Current for LED I OH2 Driver R Pull-high Resistance PH V A/D Input Voltage AD Rev. 1.20 HT46R322/HT46R342 +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Total............................................................ 100mA OH Operating Temperature: 40 C~+85 C, Ta=25 C Test Conditions Min. V Conditions DD ...
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... System Start-up Timer Period SST t Low Voltage Width to Reset LVR t Interrupt Pulse Width INT t A/D Clock Period AD t A/D Conversion Time ADC t A/D Sampling Time ADCS Note: *t =1/f SYS SYS Rev. 1.20 HT46R322/HT46R342 Test Conditions Min. V Conditions Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3 ...
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... CM PSRR Power Supply Rejection Ratio CMRR Common Mode Rejection Ratio t Response Time (Comparator) RES A.C. Electrical Characteristic V Open Loop Gain OPOS1 SR Slew Rate +, Slew Rate - GBW Gain Band Width Rev. 1.20 HT46R322/HT46R342 Test Conditions Min. V Conditions Calibration =0~V 1 ...
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... Return from Subroutine S11 Note: PC11~PC8: Current Program Counter bits #11~#0: Instruction Code bits For the HT46R322 device the Program Counter is 11 bits wide, i.e. from b10~b0, therefore the b11 column in the table is not applicable. Rev. 1.20 HT46R322/HT46R342 incremented by one. The program counter then points to the memory word containing the next instruction code ...
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... Note: *11~*0: Table location bits @7~@0: Table pointer bits For the HT46R322 device the Table address is 11 bits wide, i.e. from b10~b0, therefore the b11 column in the table is not applicable. Rev. 1.20 HT46R322/HT46R342 Program Memory - HT46R322 Program Memory - HT46R342 restored. If the main routine and the ISR, Interrupt ...
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... Purpose Data Memory is reserved for future expanded usage, reading these locations will obtain a result of 00H . The general purpose data memory, addressed from 28H to 7FH in the HT46R322, and from 40H to FFH in the HT46R342, is used for user data and control infor- mation under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly ...
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... ADF A/D converter request flag (1=active; 0=inactive) 7 Unused bit, read as 0 Rev. 1.20 HT46R322/HT46R342 tion operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the CLR WDT or HALT in- struction. The PDF flag can be affected only by exe- cuting the HALT or CLR WDT instruction or a system power-up ...
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... T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter- rupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. Rev. 1.20 HT46R322/HT46R342 These can be masked by resetting the EMI bit. Interrupt Source Priority External Interrupt ...
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... CLR WDT and the other set CLR WDT1 and CLR WDT2 . Of these two types of instruction, only one can be active depending on the Rev. 1.20 HT46R322/HT46R342 configuration option CLR WDT times selection op - tion . If the CLR WDT is selected (i.e. CLR WDT times equal one), any execution of the CLR WDT instruction will clear the WDT ...
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... Any wake-up from HALT will en- able the SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). Rev. 1.20 HT46R322/HT46R342 The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable Clear ...
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... The registers states are summarised in the following table. Reset Register (Power On) (Normal Operation HT46R322 1xxx xxxx MP - HT46R342 xxxx xxxx ACC xxxx xxxx PCL 0000 0000 TBLP xxxx xxxx TBLH - HT46R322 --xx xxxx TBLH - HT46R342 -xxx xxxx STATUS --00 xxxx INTC -000 0000 TMR ...
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... TON bit can only be reset by instructions. The clock. INT overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing ETI can disable the interrupt service. Function SYS /2 SYS /4 SYS /8 SYS /16 SYS /32 SYS /64 SYS /128 SYS TMRC (0EH) Register 15 HT46R322/HT46R342 July 11, 2007 ...
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... There are 19 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC, PD and PE, which are mapped to the data memory of [12H], [14H], Rev. 1.20 HT46R322/HT46R342 Timer/Event Counter [16H], [18H] and [1AH] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H or 1AH) ...
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... Logical Logical PD1 Input Output Input Rev. 1.20 HT46R322/HT46R342 It is recommended that unused I/O lines should be setup as output pins by software instructions to avoid consum- ing power under input floating states. PWM The microcontroller provides a 2 channel (6+2) bits PWM0/PWM1 output shared with PD0/PD1. The PWM channel has its data register denoted as PWM0 and PWM1 ...
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... A/D conversion flag. This bit is monitored to check when the A/D conversion has completed. The START bit of the ADCR register is used to initiate the A/D conversion Rev. 1.20 HT46R322/HT46R342 PWM process. When the START bit is provided with a raising edge and then a falling edge, the A/D conversion pro- cess will begin. In order to ensure that the A/D conver- ...
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... Select the A/D converter clock source SYS 0 ADCS0 SYS 1 ADCS1 /32 SYS 1, 1: Undefined 2~6 Unused bit, read TEST For internal test only. Rev. 1.20 HT46R322/HT46R342 Function ADCR (22H) Register Function ACSR (23H) Register A/D Conversion Timing 19 July 11, 2007 ...
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... START set START ; reset A/D clr START ; start A EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1.20 HT46R322/HT46R342 /8 as the A/D clock SYS /8 as the A/D clock SYS 20 July 11, 2007 ...
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... The devices include an integrated operational amplifier or comparator, selectable via configuration option. The default is function is comparator. The input voltage off- set is adjustable by using a common mode input to cali- brate the offset value. Rev. 1.20 HT46R322/HT46R342 The relationship between V Note the voltage range for proper chip OPR operation at 4MHz system clock ...
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... CLRWDT instruction(s): one or two clear WDT instruction(s) 4 System oscillator crystal 5 Pull-high resistors (PA, PB, PD): none or pull-high 6 PWM enable or disable 7 PA0~PA7 wake-up: enable or disable 8 PFD enable or disable 9 Low voltage reset selection: enable or disable LVR function. 10 Comparator or OP selection Rev. 1.20 HT46R322/HT46R342 Function OPAC (1FH) Register Options /4) SYS 22 July 11, 2007 ...
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... The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.20 HT46R322/HT46R342 HT46R322 C1 C1, C2 25pF 12k ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.20 HT46R322/HT46R342 Description 24 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... Otherwise the original instruction cycle is unchanged. (3) (1) (2) : and (4) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.20 HT46R322/HT46R342 Description 25 Instruction Flag Cycle Affected 2 None (2) 1 ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.20 PDF PDF PDF PDF PDF HT46R322/HT46R342 July 11, 2007 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.20 PDF PDF PDF addr PDF PDF HT46R322/HT46R342 July 11, 2007 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.20 PDF PDF PDF PDF PDF HT46R322/HT46R342 July 11, 2007 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.20 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT46R322/HT46R342 July 11, 2007 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.20 Program Counter+1 PDF PDF PDF addr PDF PDF HT46R322/HT46R342 July 11, 2007 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.20 PDF PDF Program Counter+1 PDF PDF PDF PDF HT46R322/HT46R342 July 11, 2007 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.20 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT46R322/HT46R342 July 11, 2007 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.20 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT46R322/HT46R342 July 11, 2007 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.20 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT46R322/HT46R342 July 11, 2007 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.20 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT46R322/HT46R342 July 11, 2007 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.20 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT46R322/HT46R342 July 11, 2007 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.20 PDF PDF PDF PDF PDF HT46R322/HT46R342 July 11, 2007 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.20 PDF PDF PDF HT46R322/HT46R342 July 11, 2007 ...
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... Package Information 44-pin QFP (10´10) Outline Dimensions Symbol Rev. 1.20 Dimensions in mm Min. Nom. 13 9.9 13 9.9 0.8 0.3 1.9 0.25 0.73 0.1 0 HT46R322/HT46R342 Max. 13.4 10.1 13.4 10.1 2.2 2.7 0.5 0.93 0.2 7 July 11, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.20 HT46R322/HT46R342 40 July 11, 2007 ...