HT46R343 Holtek Semiconductor Inc., HT46R343 Datasheet
HT46R343
Related parts for HT46R343
HT46R343 Summary of contents
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... Integrated PFD function for sound generation Power-down and wake-up functions reduce power consumption General Description The HT46R343 is 8-bit, high performance, RISC archi- tecture microcontroller devices. With their fully inte- grated A/D converter they are especially suitable for applications which interface to analog signals, such as those from sensors ...
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... Block Diagram Rev. 1.00 2 HT46R343 October 11, 2007 ...
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... PE0~PE7 can be used as LED driver (sink end). APN and APP are the internal operational amplifier, negative input pin and positive input pin respectively . Schmitt trigger reset input. Active low. Positive power supply Negative power supply, ground. 3 HT46R343 October 11, 2007 ...
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... HALT load, system HALT 5V 0 0.7V 0 0.9V 2.7 V =0. =0. =0. =0. =0. =0. HT46R343 Typ. Max. Unit 5.5 V 5.5 V 0.6 1 0.8 1 3.0 3 ...
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... Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 0 3.3V~5. Wake-up from HALT 0. HT46R343 Typ. Max. Unit 100 0 1 2.5 12 Bits Ta=25 C Typ. Max. Unit 4000 kHz ...
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... Gain Band Width Rev. 1.00 Test Conditions Min. V Conditions Calibration =0~V 1. Input overdrive= 10mV 60 No load R =1M, C =100p HT46R343 Ta=25 C Typ. Max. Unit 100 kHz October 11, 2007 ...
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... Program Counter S10 Program Counter S11~S0: Stack register bits @7~@0: PCL bits 7 HT46R343 * ...
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... At the end of a subroutine or an interrupt routine, signaled by a return instruction, Table Location * Table Location P11~P8: Current program counter bits 8 HT46R343 * October 11, 2007 ...
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... Arithmetic operations - ADD, ADC, SUB, SBC, DAA Logic operations - AND, OR, XOR, CPL Rotation - RL, RR, RLC, RRC Increment and Decrement - INC, DEC Branch decision - SZ, SNZ, SIZ, SDZ .... The ALU not only saves the results of a data operation but also changes the status register. RAM Mapping 9 HT46R343 October 11, 2007 ...
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... If the stack is full, the in- terrupt request will not be acknowledged, even if the re- lated interrupt is enabled, until the stack pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. Function Status (0AH) Register Function INTC (0BH) Register 10 HT46R343 October 11, 2007 ...
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... The system clock, di- vided by 4, can be monitored on pin OSC2 if a pull-high resistor is connected. This signal can be used to syn- chronise external logic. The RC oscillator provides the most cost effective solution, however the frequency of System Oscillator 11 HT46R343 Priority Vector 1 004H 2 008H 3 ...
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... Each bit in port A can be independently selected to wake up the device by the options. Awakening from an I/O port stim- ulus, the program will resume execution of the next in- struction awakening from an interrupt, two Watchdog Timer 12 HT46R343 CLR WDT times selection October 11, 2007 ...
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... Stack Pointer Points to the top of the stack Reset Timing Chart Reset Circuit Note: Most applications can use the Basic Reset Cir- cuit as shown, however for applications with ex- tensive noise recommended to use the Hi-noise Reset Circuit. Reset Configuration 13 HT46R343 October 11, 2007 ...
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... HT46R343 RES Reset WDT Times-out (HALT) (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 uuuu uuuu uuuu uuuu --uu uuuu ...
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... T0ON (T1ON) can only be reset by instructions. The overflow of the Timer/Event Counter is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) Function SYS /2 SYS /4 SYS /8 SYS /16 SYS /32 SYS /64 SYS /128 SYS TMR0C (0EH) Register 15 HT46R343 October 11, 2007 ...
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... Unused bits, read as 0 Defines the operating mode (T1M1, T1M0)= 01=Event count mode (external clock) 6 T1M0 10=Timer mode (internal clock) 7 T1M1 11=Pulse width measurement mode 00=Unused Rev. 1.00 Function TMR1C (11H) Register Timer/Event Counter 0 Timer/Event Counter 1 16 HT46R343 October 11, 2007 ...
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... After a device reset, the input/output lines will default to inputs and remain at a high level or floating state, de- pendent upon the pull-high configuration options. Each bit of these input/output latches can be set or cleared by the SET [m].i and CLR [m].i (m=12H, 14H, 16H, 18H or 1AH) instructions. Input/Output Ports 17 HT46R343 October 11, 2007 ...
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... PWM input clock period (6+2) bit PWM function, the contents of the PWM register is di- vided into two groups. Group 1 of the PWM register is denoted by DC which is the value of PWM.7~PWM.2. Group 2 is denoted by AC which is the value of PWM.1~PWM.0. 6+2 PWM Mode 18 HT46R343 O/P I/P O/P (PWM) (PWM) Logical Logical ...
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... START bit high and then clearing it to zero within 10 instruction cycles of the Port B, Port C channel selection bits being modified. Note that if the Port B, Port C channel selection bits are all cleared to zero then an A/D initialisation is not required. 19 HT46R343 October 11, 2007 ...
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... ACS3, ACS2, ACS1, ACS0 AN0 1000 AN1 1001 AN2 1010 AN3 1011 AN4 1100 AN5 1101 AN6 1110 AN7 1111 A/D Channel Function ACSR (23H) Register 20 HT46R343 Bit2 Bit1 Bit0 Channel AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 October 11, 2007 ...
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... AN7 AN6 AN5 AN9 AN8 AN7 AN6 AN5 AN9 AN8 AN7 AN6 AN5 AN9 AN8 AN7 AN6 AN5 Port B, C configuration A/D Conversion Timing 21 HT46R343 PB5 PB4 PB3 PB2 PB1 PB0 PB5 PB4 PB3 PB2 PB1 AN0 PB5 PB4 ...
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... START set START ; reset A/D clr START ; start A EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 1. the A/D clock SYS /8 as the A/D clock SYS 22 HT46R343 October 11, 2007 ...
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... Set the ARS bit to select which input pin is the reference voltage - closes either switch Adjust bits AOF0~AOF3 until the output status OPAOP has changed. Set AOFM=0 to select the normal operating mode 23 HT46R343 and V is shown below. DD LVR delay enter the ...
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... CLRWDT instruction(s): one or two clear WDT instruction(s) 4 System oscillator crystal 5 Pull-high resistors (PA, PB, PD): none or pull-high 6 PWM enable or disable 7 PA0~PA7 wake-up: enable or disable 8 PFD enable or disable 9 Low voltage reset selection: enable or disable LVR function. 10 Comparator or OP selection Rev. 1.00 Function OPAC (1FH) Register Options /4) SYS 24 HT46R343 October 11, 2007 ...
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... RES pin is kept as short as possible, to avoid noise interference. 3. For applications where noise may interfere with the reset circuit and for details on the oscillator external com- ponents, refer to Application Note HA0075E for more information. Rev. 1.00 25 HT46R343 October 11, 2007 ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 26 HT46R343 October 11, 2007 ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 27 HT46R343 Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 28 HT46R343 Cycles Flag Affected 1 None Note 1 ...
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... Operation ACC ACC AND x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. Operation [m] ACC AND [m] Affected flag(s) Z Rev. 1.00 29 HT46R343 October 11, 2007 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO 0 PDF 0 Affected flag(s) TO, PDF Rev. 1.00 addr 30 HT46R343 October 11, 2007 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO 0 PDF 1 Affected flag(s) TO, PDF Rev. 1. HT46R343 October 11, 2007 ...
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... No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. Operation ACC ACC OR [m] Affected flag(s) Z Rev. 1.00 addr 32 HT46R343 October 11, 2007 ...
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... The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) None Rev. 1.00 Stack Stack Stack [m]. 0~6) 33 HT46R343 October 11, 2007 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i [m].(i+1 0~6) ACC [m].0 Affected flag(s) C Rev. 1.00 [m]. 0~6) 34 HT46R343 October 11, 2007 ...
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... Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i 1 Affected flag(s) None Rev. 1.00 [ HT46R343 October 11, 2007 ...
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... The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC ACC Affected flag(s) OV, Z, AC, C Rev. 1.00 0 [m] [ HT46R343 October 11, 2007 ...
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... The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] program code (low byte) TBLH program code (high byte) Affected flag(s) None Rev. 1.00 [m].7 ~ [m].4 [m].7 ~ [m].4 [m].3 ~ [m].0 37 HT46R343 October 11, 2007 ...
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... The result is stored in the Data Memory. Operation [m] ACC XOR [m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC ACC XOR x Affected flag(s) Z Rev. 1.00 38 HT46R343 October 11, 2007 ...
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... Package Information 44-pin QFP (10´10) Outline Dimensions Symbol Rev. 1.00 Dimensions in mm Min. Nom. 13 9.9 13 9.9 0.8 0.3 1.9 0.25 0.73 0.1 0 HT46R343 Max. 13.4 10.1 13.4 10.1 2.2 2.7 0.5 0.93 0.2 7 October 11, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 40 HT46R343 October 11, 2007 ...