HT56R66 Holtek Semiconductor Inc., HT56R66 Datasheet - Page 62

• Manufacturer Part Number: HT56R66
• Description: Tinypower Tm A/d Type With Lcd 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

I
The SIMARregister is also used by the SPI interface but
has the name SIMCTL2.
The SIMARregister is the location where the 7-bit slave
address of the microcontroller is stored. Bits 1~7 of the
SIMAR register define the microcontroller slave ad-
dress. Bit 0 is not defined. When a master device, which
is connected to the I
which matches the slave address in the SIMARregister,
the microcontroller slave device will be selected. Note
that the SIMAR register is the same register as
SIMCTL2 which is used by the SPI interface.
I
Communication on the I
steps, a START signal, a slave device address transmis-
sion, a data transmission and finally a STOP signal.
When a START signal is placed on the I
vices on the bus will receive this signal and be notified of
the imminent arrival of data on the bus. The first seven
bits of the data will be the slave address with the first bit
being the MSB. If the address of the microcontroller
matches that of the transmitted address, the HAAS bit in
the SIMCTL1 register will be set and an I
be generated. After entering the interrupt service rou-
tine, the microcontroller slave device must first check
the condition of the HAAS bit to determine whether the
interrupt source originates from an address match or
from the completion of an 8-bit data transfer. During a
data transfer, note that after the 7-bit slave address has
been transmitted, the following bit, which is the 8th bit, is
the read/write bit whose value will be placed in the SRW
bit. This bit will be checked by the microcontroller to de-
termine whether to go into transmit or receive mode. Be-
fore any transfer of data to or from the I
microcontroller must initialise the bus, the following are
steps to achieve this:
Step 1
Write the slave address of the microcontroller to the I
bus address register SIMAR.
Step 2
Set the SIMEN bit in the SIMCTL0 register to 1 to en-
able the I
Step 3
Set the ESIM bit of the interrupt control register to en-
able the I
Rev. 1.10
2
2
C Control Register - SIMAR
C Bus Communication
2
2
C bus.
C bus interrupt.
2
C bus, sends out an address,
2
C bus requires four separate
I
2
2
C Slave Address Register - SIMAR
2
C interrupt will
C bus, all de-
2
C bus, the
2
C
62
Start Signal
The START signal can only be generated by the mas-
ter device connected to the I
microcontroller, which is only a slave device. This
START signal will be detected by all devices con-
nected to the I
that the I
be set. A START condition occurs when a high to low
transition on the SDA line takes place when the SCL
line remains high.
Slave Address
The transmission of a START signal by the master will
be detected by all devices on the I
mine which slave device the master wishes to com-
municate with, the address of the slave device will be
sent out immediately following the START signal. All
slave devices, after receiving this 7-bit address data,
will compare it with their own 7-bit slave address. If the
address sent out by the master matches the internal
address of the microcontroller slave device, then an
internal I
next bit following the address, which is the 8th bit, de-
fines the read/write status and will be saved to the
SRW bit of the SIMCTL1 register. The device will then
transmit an acknowledge bit, which is a low level, as
the 9th bit. The microcontroller slave device will also
set the status flag HAAS when the addresses match.
As an I
when the program enters the interrupt subroutine, the
HAAS bit should be examined to see whether the in-
terrupt source has come from a matching slave ad-
dress or from the completion of a data byte transfer.
When a slave address is matched, the device must be
placed in either the transmit mode and then write data
to the SIMDR register, or in the receive mode where it
must implement a dummy read from the SIMDR regis-
ter to release the SCL line.
2
C bus interrupt can come from two sources,
I
2
2
2
C bus interrupt signal will be generated. The
C bus is busy and therefore the HBB bit will
C Bus Initialisation Flow Chart
2
C bus. When detected, this indicates
HT56R66/HT56R666
2
C bus and not by the
September 8, 2009
2
C bus. To deter-