DSPIC33FJ12GP202 Microchip Technology Inc., DSPIC33FJ12GP202 Datasheet - Page 161
DSPIC33FJ12GP202
Manufacturer Part Number
DSPIC33FJ12GP202
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ12GP202.pdf
(242 pages)
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REGISTER 16-2:
© 2007 Microchip Technology Inc.
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character (character at the top of the receive
0 = Framing error has not been detected
OERR: Receive Buffer Overrun Error Status bit (read/clear only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1 → 0 transition) will reset
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
FIFO)
the receiver buffer and the UxRSR to the empty state
U
x
STA: UART
x
STATUS AND CONTROL REGISTER (CONTINUED)
Preliminary
dsPIC33FJ12GP201/202
DS70264B-page 159
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