S5K433LA Samsung Semiconductor, Inc., S5K433LA Datasheet - Page 17

• Manufacturer Part Number: S5K433LA
• Description: 1/4 Optical Size 640x480 Vga 3.3v/2.8v Vga Cmos Image Sensor
• Manufacturer: Samsung Semiconductor, Inc.

1/4 INCH VGA CMOS IMAGE SENSOR
OPERATION DESCRIPTION
1. Output Data Format
1-1. Main Clock Divider
input main clock (MCLK). The dividing ratio is 1, 2, 4, and 8 according to main clock dividing control register
(mcdiv). For 10-bit ADC and VGA resolution, dividing ratio of more than 2 is required. If ratio of 1 is used, the duty
must be within 40% to 60%.
1-2. Synchronous Signal Output
and position are programmable by control registers (ref. timing chart). When display mode is enabled, the sync
signal outputs indicate that the output data is valid (hsdisp=1) or the output rows are valid (vsdisp=1).
1-3. Window of Interest Control
anywhere on the pixel array. It is composed of four values: row start pointer(wrp), column start pointer(wcp), row
depth(wrd) and column width(wcw). Each value can be programmed by control registers. For convenience of
color signal processing, wcp is truncated to even numbers so that the starting data of each line is the red and
green column of Bayer pattern. Figure 4 refers to a pictorial representation of the WOI on the displayed pixel
image.
normally. By changing the mirror mode, the read-out sequence can be reversed and the resulting image can be
flipped like a mirror image. Pixel data are read out from right to left in horizontal mirror mode and from bottom to
top in vertical mirror mode. The horizontal and the vertical mirror mode can programmed by Horizontal Mirror
Control Register (mirch) and Vertical Mirror Control Register (mircv).
1-5. Sub-sampling Control
can be done in four rates : full, 1/2, 1/3 and 1/4. The user controls the sub-sampling using the Sub-sampling
Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space.
1-4. Vertical Mirror and Horizontal Mirror Mode Control
The user can read out the pixel data in sub-sampling rate in both horizontal and vertical direction. Sub-sampling
All the data output and sync signals are synchronized to data clock output (DCLK). It is generated by dividing the
The horizontal sync(HSYNC) and vertical sync(VSYNC) signals are also available. The sync pulse width, polarity
Window of Interest (WOI) is defined as the pixel address range to be read out. The WOI can be assigned
The pixel data are read out from left to right in horizontal direction and from top to bottom in vertical direction
507
0
(wcp,wrp)
0
Window Of Interest
Figure 4. WOI definition.
wcw
687
S5K433CA, S5K433LA
17