CY25200 Cypress Semiconductor Corporation., CY25200 Datasheet
CY25200
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CY25200 Summary of contents
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... Bank 1 VCO P Divider Bank 2 PLL AVSS VSS VDD AVDD VDDL VSSL CP0 • 198 Champion Court • San Jose CY25200 7 SSCLK1 8 SSCLK2 Output 9 SSCLK3 Select Matrix 12 SSCLK4 14 SSCLK5/REFOUT/CP2 15 SSCLK6/REFOUT/CP3 10 CP1 , CA 95134-1709 • 408-943-2600 Revised December 11, 2007 Load [+] Feedback ...
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... The range for down spread is from –0.5% to –5.0%. Contact the factory for smaller or larger spread % amounts, if required. The input to the CY25200 is either a crystal or a clock signal. The input frequency range for crystals is 8–30 MHz and for clock signals is 8–166 MHz. ...
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... ENTER DATA CLKSEL = 1 Programming Description Field-Programmable CY25200 The CY25200 is programmed at the package level, that is programmer socket. The CY25200 is Flash technology based, so the parts are reprogrammed up to 100 times. This allows for fast and easy design changes and product updates, and elimi- nates any issues with old and out of date inventory ...
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... However, they can also be used as control signals. See Figure 3 Input Frequency (XIN, pin 1 and XOUT, pin 16) The input to the CY25200 is a crystal or a clock. The input fre- quency range for crystals MHz, and for clock signal 166 MHz. C ...
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... XOUT 1 16 14.318MHz 15 VDD 2 REFOUT(14.318MHz) 14 AVDD 3 REFOUT(14.318MHz) 13 VSS CLKSEL 4 12 AVSS 33.33/66.66MHz 5 11 VSSL VDDL 6 10 33.33/66.66MHz SSON 7 9 33.33/66.66MHz 8 33.33/66.66MHz CY25200 SSCLK4 REFOUT REFOUT (Pin 12) (Pin 14) (Pin 15) 33.33 14.318 14.318 66.66 14.318 14.318 Page [+] Feedback [+] Feedback ...
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... Figure 4. Duty Cycle Timing ( )/SR1 (or SR3) DD )/SR2 (or SR4) DD Figure 6. Power Down and Power Up Timing High Impedance t STP Figure 7. Output Enable and Disable Timing OE2 V IL High Impedance T OE1 a CY25200 / Page [+] Feedback [+] Feedback ...
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... Fnominal 65.5 65 64 160 180 200 67.5 67 66.5 66 Fnominal 65 160 180 200 CY25200 Fmod=30kHz, Spread%= -4% Fnominal 100 120 140 160 180 200 Time (us) Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1% Fnominal 100 120 140 160 180 200 Time (us) Page ...
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... DD DDL = 2.5V DDL = 3 VDD DDL = A = 3.3.V and V = 2.5V DD VDD DDL = A = 3.3.V and V = 3.3V or 2.5V DD VDD DDL s to reach minimum specified voltage DD CY25200 Min Typ. Max Unit 8 30 MHz values are much Min Typ. Max Unit 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2 ...
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... DD CMOS levels, 30 Current Current (V = 2.625V) DDL DDL V Current (V = 3.465V) DDL DDL 3.465V DD DDL 3.465V DD DDL DD CY25200 Min Typ. Max Unit 10 12 – – – – mA 0.7 – 1 – 0 – – ...
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... Time from rising edge outputs at a valid frequency (Asynchronous) SSCLK1/2/3/4/5/6 Time from rising edge on PD# to outputs at valid frequency (Asynchronous) Time from rising edge on PD# to outputs at valid frequency (Asynchronous) Output to output skew between related clock outputs. Measured at V /2. DD CY25200 Min Typ. Max Unit ...
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... Ordering Information [6] Ordering Code CY25200ZXC_XXXW 16-lead TSSOP (Pb Free) CY25200ZXC_XXXWT 16-lead TSSOP – Tape and Reel (Pb Free) CY25200FZXC 16-lead TSSOP (Pb Free) CY25200FZXCT 16-lead TSSOP – Tape and Reel (Pb Free) CY3672 FTG Development Kit CY3672-PRG FTG Programmer CY3695 CY22050F/CY22150F/CY25200F Socket Adapter Table 5. 16-lead TSSOP Package Characteristics Parameter θ ...
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... Document History Page Document Title: CY25200 Programmable Spread Spectrum Clock Generator for EMI Reduction Document Number: 38-07633 REV. ECN NO. Issue Date ** 204243 See ECN *A 220043 See ECN *B 267832 See ECN *C 291094 See ECN *D 1821908 See ECN DPF/AESA Corrected FSSCLK-Low Voltage specification on page 7 for SSCLK5/6 to © ...