CY23FS08-04 Cypress Semiconductor Corporation., CY23FS08-04 Datasheet
CY23FS08-04
Related parts for CY23FS08-04
CY23FS08-04 Summary of contents
Page 1
... The unique feature of the CY23FS08-04 is that the DCXO is in fact, the primary clocking source, that is synchronized (phase aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock ...
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... VSSB 20 VSSA 10 CLKB3 19 CLKA3 11 CLKB4 18 CLKA4 12 VDDB 17 VDDA 13 VDDC 16 FAIL#/SAFE 14 15 XIN XOUT 28-pin SSOP Description [3] . [1] CLKB3 and CLKB4 are differential signals when terminated as Figure 8 on page 6. CLKB3 is negtive output, CLKB4 is positive output. [1] [2] CY23FS08-04 [3] Page [+] Feedback [+] Feedback ...
Page 3
... The technique implemented in this design completely eliminates any switching of references to the PLL that greatly simplifies the system design. The CY23FS08-04 PLL is driven by the crystal oscillator that is phase aligned to an external reference clock aligned in a way that the output of the device is effectively phase aligned to reference via the external feedback loop ...
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... Fail#/Safe Deassert Delay FSH DCXO and capture range Failsafe has DCXO for tracking to incoming reference clock. The CY23FS08-04 is configured its capture range of approx +/- 100ppm with using pullable crystal that specified in Figure 4. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range ...
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... Figure 5. FailSafe Reference Switching Behavior Failsafe typical frequency settling time 150 100 Figure 6. FailSafe Effective Loop Bandwidth (Min) Document Number: 001-17042 Rev. ** Initial valid Ref1 = 20 MHz +100 ppm, then switching to REF2 = 20 MHz 0.45 1.3 SETTLING TIME (ms) CY23FS08-04 2.5 Page [+] Feedback [+] Feedback ...
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... Typical Settling Time (105 MHz CY23FS08- Page [+] Feedback [+] Feedback ...
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... (φ (φ ) CY23FS08- Page [+] Feedback [+] Feedback ...
Page 8
... V (100k pull up only (100k pull down only 0.5V 1. – 0.5V 1. and V are all at the maximum values, DDB DDC = 0mA, output frequency = maximum CY23FS08-04 Min Max Unit –0.5 4.6 V –0.5 V +0.5 VDC DD –65 +150 °C –40 85 °C 125 °C 2000 V 36 ...
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... Measured from 20 1.8V Load DD All outputs equally loaded, measured at V All outputs equally loaded, measured at V Measured Measured ≥ 6.25 MHz Load = 15 pF, f OUT Description CY23FS08-04 Min Typ Max 1.0 – 4.1 MHz 1.0 – 133 MHz 15 – 25 MHz 40 – ...
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... Package Drawing and Dimensions Figure 10. 28-Pin (5.3 mm) Shrunk Small Outline Package O28 Document Number: 001-17042 Rev. ** Package Type 28-pin SSOP 28-pin SSOP – Tape and Reel CY23FS08-04 Product Flow Industrial, –40°C to 85°C Industrial, –40°C to 85°C 51-85079-*C Page ...
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... Document History Page Document Title: CY23FS08-04 FailSafe™ 1.8V Zero Delay Buffer Document Number: 001-17042 Issue Orig. of REV. ECN NO. Date Change ** 1493204 See ECN XHT/WWZ/ © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...