CY24271 Cypress Semiconductor Corporation., CY24271 Datasheet
CY24271
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CY24271 Summary of contents
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... • 198 Champion Court • San Jose CY24271 95134-1709 • 408-943-2600 ...
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... REFCLK bypassing PLL (CMOS signal) Power supply for outputs Complement clock output Clock output Ground Complement clock output Clock output Ground Power supply for outputs Complement clock output Clock output Ground Complement clock output Clock output Power supply for outputs CY24271 Page [+] Feedback [+] Feedback ...
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... CY24271 devices on the same SMBus. Modes of Operation The modes of operation are determined by the logic signals applied to the EN and /BYPASS pins and the values in the five Table 3. SMBus Device Addresses for CY24271 XCG Hex Address Device Operation ...
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... Conditions on page 7, the outputs also meet the DC and AC Operating Conditions tables. SMBus Data Byte Definitions Three data bytes are defined for the CY24271. Byte 0 is for programming the PLL multiplier registers and clock output registers. The definition of Byte 2 is shown in on page 5 ...
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... Reserved (must be set to ‘0’ for proper operation) RW Reserved (must be set to ‘0’ for proper operation) Type Description RO Contact factory for Device Revision Number information RAMBUS assigned Vendor ID Code RO RO Table 2 for PLL multipliers and CY24271 Table 2) Table 4 for clock output selections. Page [+] Feedback [+] Feedback ...
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... ESD ESD Protection (Human Body Model) MIL-STD-883, Method 3015 HBM Document Number: 001-00411 Rev. *B Supply Voltage V REFCLK Condition Relative Relative Relative Non-functional Functional Functional CY24271 TH Input XDR Clock Generator Single-ended Input Min Max Unit –0.5 4.6 V –0.5 4.6 V –0.5 4.6 V –0.5 4 ...
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... Not 100% tested except V . Parameters guaranteed by design and characterizations, not 100% tested in production. IXCLK IXCLK 8. This range of SCL and SDA input high voltage enables the 3.3V, 2.5V, or 1.8V SMBus voltages to use CY24271. 9. Single-ended operation guaranteed only when 0.8 < (V Document Number: 001-00411 Rev. *B Condition 2.5V ± 5% 2.5V ± ...
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... MHz, and f = 667 MHz ref out = 133 MHz, and f = 800 MHz ref out [17] [18] [19 148 ohms or less. RC – under conditions specified for I 0.94 0.90 OL, ABS CY24271 Min Max Unit – ns – 185 ps 40% 60% t CYCLE 175 ...
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... Figure 3. Clock Outputs V TS Measurement R Point 1 CLK Differential Driver Measurement R Point 1 CLKB CY24271 Min Typ Max Unit 1.25 3.34 ns – – – –135 –128 dBC/Hz – – TBD – – – ...
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... Cycle-to-cycle duty cycle is defined as the difference between t (high times) of adjacent differential clock cycles. Equal PW+ requirements apply to t cycles. Figure 4. Input and Output Waveforms Figure 5. Crossing Point Voltage CY24271 . is larger than Figure 6 Figure 7 shows the duty cycle error (t ...
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... CLKB t t DC,ERR Document Number: 001-00411 Rev. *B Figure 6. Cycle-to-cycle Jitter t CYCLE,i CYCLE,i CYCLE,i+1 over 10,000 consecutive cycles Figure 7. Cycle-to-cycle Duty-cycle Error (i) t (i+1) t (i) PW- PW- PW+ t (i+1) t (i) CYCLE, CYCLE ( (i+1) and t PW- PW- PW- CY24271 t (i+1) PW+ (i+ (i+1) PW+ Page [+] Feedback [+] Feedback ...
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... PIN 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 28 1.10[0.043] MAX. 0.19[0.007] 0.30[0.012] GAUGE PLANE 0.076[0.003] 0.05[0.002] SEATING 0.15[0.006] PLANE CY24271 Product Flow Commercial, 0°C to 70°C Commercial, 0°C to 70°C 0.25[0.010] BSC 0°-8° 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85120-*A Page [+] Feedback [+] Feedback ...
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... Document History Page Document Title: CY24271 Rambus XDR Clock Generator Document Number: 001-00411 Issue Orig. of REV. ECN NO. Date Change ** 378263 See ECN RGL *A 492065 See ECN KKVTMP 1) New Pin definition table *B 1333483 See ECN FGA/SFV Added IDD values in DC Electrical Specifications table © ...