MIC2778 Micrel Semiconductor, MIC2778 Datasheet - Page 22

• Manufacturer Part Number: MIC2778
• Description: Mic2778 Voltage Monitor With Adjustable Hysteresis
• Manufacturer: Micrel Semiconductor

Detailed Register Descriptions
Control Register, Slot A (CNTRLA)
8-Bits, Read/Write
The power-up default value is 00h. Slot is disabled upon power-up, i.e., all supply outputs are off.
Notes:
1.
March 2005
/FORCE_A
/FORCE_A
/FORCE_A
MAINAPG
MAINAPG
MAINAPG
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
AUXAPG
ENABLE
ENABLE
ENABLE
VAUXA
VAUXA
VAUXA
MAINA
MAINA
MAINA
The state of the /PWRGDA pin is the logical AND of the values of the AUXAPG and the MAINAPG bits, except when /FORCE_ONA is asserted. If
/FORCE_ONA is asserted (the pin is pulled low), and /FORCE_AENABLE is set to a logic zero, the /PWRGDA pin will be unconditionally forced to
its open-drain (“Power Not Good”) state.
Bit(s)
Bit(s)
Bit(s)
D[7]
D[7]
D[7]
D[7]
D[7]
D[7]
D[7]
D[7]
D[5]
D[5]
D[5]
D[4]
D[4]
D[4]
D[3]
D[3]
D[3]
Power-Up Default Value:
Read Command_Byte Value (R/W):
AUX output power-good status, Slot A
AUX output power-good status, Slot A
AUX output power-good status, Slot A
MAIN output power-good status, Slot A
MAIN output power-good status, Slot A
MAIN output power-good status, Slot A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Allows or inhibits the operation of the /FORCE_ONA
Allows or inhibits the operation of the /FORCE_ONA
Allows or inhibits the operation of the /FORCE_ONA
input pin
input pin
input pin
MAIN enable control, Slot A
MAIN enable control, Slot A
MAIN enable control, Slot A
VAUX enable control, Slot A
VAUX enable control, Slot A
VAUX enable control, Slot A
MAINAPG
MAINAPG
MAINAPG
MAINAPG
MAINAPG
MAINAPG
MAINAPG
MAINAPG
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
D[6]
D[6]
D[6]
D[6]
D[6]
D[6]
D[6]
D[6]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
read only
read only
read only
read only
read only
read only
read only
read only
Function
Function
Function
D[5]
D[5]
D[5]
D[5]
D[5]
D[5]
D[5]
D[5]
Control Register, Slot A (CNTRLA)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
read only
read only
read only
read only
read only
read only
read only
read only
D[4]
D[4]
D[4]
D[4]
D[4]
D[4]
D[4]
D[4]
0000 0000b = 00h
0000 0010b = 02h
22
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
read-only
read-only
read-only
read-only
read-only
read-only
read-only
read-only
D[3]
D[3]
D[3]
D[3]
D[3]
D[3]
D[3]
D[3]
1 = Power-is-Good
1 = Power-is-Good
1 = Power-is-Good
(VAUXA Output is above its UVLO threshold)
(VAUXA Output is above its UVLO threshold)
(VAUXA Output is above its UVLO threshold)
1 = Power-is-Good
1 = Power-is-Good
1 = Power-is-Good
(MAINA Outputs are above their UVLO
(MAINA Outputs are above their UVLO
(MAINA Outputs are above their UVLO
thresholds)
thresholds)
thresholds)
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
Always read as zero
0 = /FORCE_ONA is enabled
0 = /FORCE_ONA is enabled
0 = /FORCE_ONA is enabled
1 = /FORCE_ONA is disabled
1 = /FORCE_ONA is disabled
1 = /FORCE_ONA is disabled
0 = Off, 1 = On
0 = Off, 1 = On
0 = Off, 1 = On
0 = Off, 1 = On
0 = Off, 1 = On
0 = Off, 1 = On
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
/FORCE_A
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
ENABLE
D[2]
D[2]
D[2]
D[2]
D[2]
D[2]
D[2]
D[2]
Operation
Operation
Operation
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
MAINA
MAINA
MAINA
MAINA
MAINA
MAINA
MAINA
MAINA
D[1]
D[1]
D[1]
D[1]
D[1]
D[1]
D[1]
D[1]
read/write
read/write
read/write
read/write
read/write
read/write
read/write
read/write
M9999-033105
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
VAUXA
D[0]
D[0]
D[0]
D[0]
D[0]
D[0]
D[0]
D[0]